Registers 0xC0~0xFF set crosspoint switching between any input channel to any internal histogram. Register address defines number of internal histogramer (lowest address is for histogram #0, next address - histogram #1, etc). Value of register defines input channel number.

Reg 0xC0 - sets the number of input channel for histogram #0, R/W

Reg 0xC1 - sets the number of input channel for histogram #1, R/W

Reg 0xC2 - sets the number of input channel for histogram #2, R/W

Reg 0xC3 - sets the number of input channel for histogram #3, R/W

Reg 0xC4 - sets the number of input channel for histogram #4, R/W

Reg 0xC5 - sets the number of input channel for histogram #5, R/W

Reg 0xC6 - sets the number of input channel for histogram #6, R/W

Reg 0xC7 - sets the number of input channel for histogram #7, R/W

Reg 0xC8 - sets the number of input channel for histogram #8, R/W

Reg 0xC9 - sets the number of input channel for histogram #9, R/W

Reg 0xCA - sets the number of input channel for histogram #10, R/W

Reg 0xCB - sets the number of input channel for histogram #11, R/W

Reg 0xCC - sets the number of input channel for histogram #12, R/W

Reg 0xCD - sets the number of input channel for histogram #13, R/W

Reg 0xCE - sets the number of input channel for histogram #14, R/W

Reg 0xCF - sets the number of input channel for histogram #15, R/W

Registers 0x100~1FF are for Gate logic LUTs.

Each gate has it own LUT. Number of MemIO words for each LUT depends on the number of external count conditions (N_EXT_CE, Input CSR register 0xF): if N_EXT_CE is 4 of less, then number of RegIO words per LUT is 1, else use equation 2^(N_EXT_CE-4). There are no empty space between LUTs.

Assume that number of external count conditions is N, and in given time moment state of external count conditions is M. Steps to resolve LUT for each gate (LUT offset is known):

determine RegIO word number: (N>4) ? 2^(N-1)-1 : 0
determine exact output bit in word from previous step: M%16

Stream readout CSR

Base address - 0x400, address mask - 0x1FF.
SDB Device ID 0xfd880c84

Reg 0x0 - Control, R/W

[14] - apply histogram count enable mask for stream encoder
[15] - enable stream

Reg 0x1 - External count enable monitor mask, R/W

Reg 0x3 - Stream packet build timeout (in milliseconds), R/W

Reg 0x6 - Slicetimer (in nanoseconds), 32-bits, R/W

Reg 0x20 - Clock frequency in KHz, 32-bits, RO

Reg 0x22 - counters width (CNT_BITS), RO

Cycle counters CSR

Base address - 0x800, address mask - 0x1FF
SDB Device ID 0x77268a46

Reg 0x0 - Control, R/W

[0] - softclear
[1] - counters lock

Reg 0x1 - Number of channels, RO

Reg 0x4 - Current state of cycles, 64-bits, RO

Start from address 0x10 groups of cycle counters are placed. One group - one histogram channel. Each group size is 16 addresses. All registers are read only

Regs 0x10~0x1F - Histogram #0 registers group

Reg 0x10 - counts during active gate, 32-bits, RO
Reg 0x12 - counts for full cycle (active + inactive gate), 32-bits, RO
Reg 0x14 - last gate start time, TAI 64-bit Timestamp, 64-bits, RO
Reg 0x18 - last gate end time, TAI 64-bit Timestamp, 64-bits, RO
Reg 0x1C - gate number, 32-bits, RO
Reg 0x1E - reserved
Reg 0x1F - reserved

Regs 0x20~0x2F - Histogram #1 registers group

...

Regs 0x100~0x10F - Histogram #15 registers group

WhiteRabbit status registers

Base address - 0x1000, address mask - 0xFF
SDB Device ID 0x6dbf32d6
WhiteRabbit status registers

Board Level Registers

MSC Onboard CSR

Base address - 0x4000, address mask - 0xFF.
SDB Device ID 0xc3bcc4aa

Reg 0x0 - Control, R/W

[0] - softclear
[1] - counters lock

Reg 0x1 - External clock status, RO

[0] - logic 1
[1] - VXS clock ok

MCU Registers

Base address - 0x4100, address mask - 0xFF.
SDB Device ID 0x47567e3c
MCU Registers

Threshold DACs setup

Base address - 0x4200, address mask - 0xFF.
SDB Device ID 0x3524236a

Reg 0x0 - Thresholds setup for channels 0..7, R/W

[15:0] DAC data

Reg 0x1 - Thresholds setup for channels 8..15, R/W

[15:0] DAC data

HWIP errors counters

Base address - 0x4300, address mask - 0xFF.
SDB Device ID 0x2a2a5a63
HWIP Error Counters

Other Registers

DDR3 CSR

Base address - 0x6000, address mask - 0xFF
SDB Device ID 0xf6a4e20c
DDR3 Stream FIFO CSR v1