<> = MSC16VE module registers v2 = Hardware: [[MSC16VE]] Memory address map: [[MSC16VE Memory Adress Map v2|MSC16VE Memory Address Map v2]] Registers are 16 bit width. 32-bit and 64-bit data is packed as following: ||Reg #||64-bit word|| ||0x70||bits 15:0|| ||0x71||bits 31:16|| ||0x72||bits 47:32|| ||0x73||bits 63:48|| == Register I/O == ||<-32 rowclass="bits">[[#SYS_REGS|System Registers]], 0x0000~0x3FFF|| ||<:>Address range||<:>Description || || 0x40-0x5F || [[TADC CSR|M-Link CSR]] || || 0x200~0x3FF || [[#MSC_IN|Input CSR]] || || 0x400~0x5FF || [[#STR|Stream readout CSR]] || || 0x600~0x7FF || [[MSC Histograms CSR v2.0]] || || 0x800~0x9FF || [[#CYCLE_CNTR|Cycle counters CSR]] || || 0x1000~0x10FF || [[WR_Status_Registers|WhiteRabbit status registers]] || ||<-32 rowclass="bits">[[#BOARD_REGS|Board Level Registers]], 0x4000~0x4FFF|| || 0x4000~0x40FF || [[#BRD_CSR|MSC onboard CSR]] || || 0x4100~0x41FF || [[MCU Registers v2.0|MCU Registers]] || || 0x4200~0x42FF || [[#THR_DAC|Threshold DACs]] || || 0x4300~0x43FF || [[HWIP_Error_Counters|HWIP Error Counters]] || ||<-32 rowclass="bits">[[#OTHER_REGS|Other Registers]], 0x6000~0x7FFF|| || 0x6000~0x60FF || [[#DDR3|DDR3 CSR]] || || 0x7000~0x70FF || [[SPI_NOR_Flash_Programmer|Flash Programmer]]|| || 0x7C00~0x7FFF || [[CategorySDB|SDB]]|| ---- ---- <> == System Registers == <> === M-Link CSR === * '''Base address - 0x40, address mask - 0x1F.''' * SDB Device ID 0x50b1d9c7 * [[TADC CSR]] <> === Input CSR === * '''Base address - 0x200, address mask - 0x1FF.''' * SDB Device ID 0xd26e4053 Reg 0x0 - Control, R/W . [1] - counters lock Reg 0x1 - Current state of external CE (TTL), RO Reg 0x2 - Current state of input HITs, RO Reg 0xD - Number of input hit channels, RO Reg 0xE - Number of histogramers, RO Reg 0xF - Number of external CE inputs, RO ''In __registers 0x80~0xBF__ times of last rising and falling edges of each external CE signal are stored. Time encoded in [[TAI 64-bit Timestamp]].'' Reg 0x80 - rising edge time of external CE #0, 64-bits, RO Reg 0x84 - falling edge time of external CE #0, 64-bits, RO Reg 0x88 - rising edge time of external CE #1, 64-bits, RO Reg 0x8C - falling edge time of external CE #1, 64-bits, RO Reg 0x90 - rising edge time of external CE #2, 64-bits, RO Reg 0x94 - falling edge time of external CE #2, 64-bits, RO Reg 0x98 - rising edge time of external CE #3, 64-bits, RO Reg 0x9C - falling edge time of external CE #3, 64-bits, RO ''__Registers 0xC0~0xFF__ set crosspoint switching between any input channel to any internal histogram. Register address defines number of internal histogramer (lowest address is for histogram #0, next address - histogram #1, etc). Value of register defines input channel number.'' Reg 0xC0 - sets the number of input channel for histogram #0, R/W Reg 0xC1 - sets the number of input channel for histogram #1, R/W Reg 0xC2 - sets the number of input channel for histogram #2, R/W Reg 0xC3 - sets the number of input channel for histogram #3, R/W Reg 0xC4 - sets the number of input channel for histogram #4, R/W Reg 0xC5 - sets the number of input channel for histogram #5, R/W Reg 0xC6 - sets the number of input channel for histogram #6, R/W Reg 0xC7 - sets the number of input channel for histogram #7, R/W Reg 0xC8 - sets the number of input channel for histogram #8, R/W Reg 0xC9 - sets the number of input channel for histogram #9, R/W Reg 0xCA - sets the number of input channel for histogram #10, R/W Reg 0xCB - sets the number of input channel for histogram #11, R/W Reg 0xCC - sets the number of input channel for histogram #12, R/W Reg 0xCD - sets the number of input channel for histogram #13, R/W Reg 0xCE - sets the number of input channel for histogram #14, R/W Reg 0xCF - sets the number of input channel for histogram #15, R/W '' __Registers 0x100~1FF__ are for Gate logic LUTs. Each gate has it own LUT. Number of MemIO words for each LUT depends on the number of external count conditions (N_EXT_CE, [[MSC16VE-EthRegisters_v2#MSC_IN|Input CSR]] register 0xF): if N_EXT_CE is 4 of less, then number of RegIO words per LUT is 1, else use equation 2^(N_EXT_CE-4). There are no empty space between LUTs. Assume that number of external count conditions is N, and in given time moment state of external count conditions is M. Steps to resolve LUT for each gate (LUT offset is known): 1. determine RegIO word number: (N>4) ? 2^(N-1)-1 : 0 2. determine exact output bit in word from previous step: M%16 '' <> === Stream readout CSR === * '''Base address - 0x400, address mask - 0x1FF.''' * SDB Device ID 0xfd880c84 Reg 0x0 - Control, R/W . [14] - apply histogram count enable mask for stream encoder . [15] - enable stream Reg 0x1 - External count enable monitor mask, R/W Reg 0x3 - Stream packet build timeout (in milliseconds), R/W Reg 0x6 - Slicetimer (in nanoseconds), 32-bits, R/W Reg 0x20 - Clock frequency in KHz, 32-bits, RO Reg 0x22 - counters width (CNT_BITS), RO <> === Cycle counters CSR === * '''Base address - 0x800, address mask - 0x1FF''' * SDB Device ID 0x77268a46 Reg 0x0 - Control, R/W . [0] - softclear . [1] - counters lock Reg 0x1 - Number of channels, RO Reg 0x4 - Current state of cycles, 64-bits, RO ''__Start from address 0x10__ groups of cycle counters are placed. One group - one histogram channel. Each group size is 16 addresses. All registers are read only'' Regs 0x10~0x1F - Histogram #0 registers group . Reg 0x10 - counts during active gate, 32-bits, RO . Reg 0x12 - counts for full cycle (active + inactive gate), 32-bits, RO . Reg 0x14 - last gate start time, [[TAI 64-bit Timestamp]], 64-bits, RO . Reg 0x18 - last gate end time, [[TAI 64-bit Timestamp]], 64-bits, RO . Reg 0x1C - gate number, 32-bits, RO . Reg 0x1E - reserved . Reg 0x1F - reserved Regs 0x20~0x2F - Histogram #1 registers group ... Regs 0x100~0x10F - Histogram #15 registers group === WhiteRabbit status registers === * '''Base address - 0x1000, address mask - 0xFF''' * SDB Device ID 0x6dbf32d6 * [[WR_Status_Registers|WhiteRabbit status registers]] ---- ---- <> == Board Level Registers == <> <> === MSC Onboard CSR === * '''Base address - 0x4000, address mask - 0xFF.''' * SDB Device ID 0xc3bcc4aa Reg 0x0 - Control, R/W . [0] - softclear . [1] - counters lock Reg 0x1 - External clock status, RO . [0] - logic 1 . [1] - VXS clock ok === MCU Registers === * '''Base address - 0x4100, address mask - 0xFF.''' * SDB Device ID 0x47567e3c * [[MCU Registers v2.0|MCU Registers]] <> === Threshold DACs setup === * '''Base address - 0x4200, address mask - 0xFF.''' * SDB Device ID 0x3524236a Reg 0x0 - Thresholds setup for channels 0..7, R/W . [15:0] DAC data Reg 0x1 - Thresholds setup for channels 8..15, R/W . [15:0] DAC data === HWIP errors counters === * '''Base address - 0x4300, address mask - 0xFF.''' * SDB Device ID 0x2a2a5a63 * [[HWIP_Error_Counters|HWIP Error Counters]] ---- ---- <> == Other Registers == <> === DDR3 CSR === * '''Base address - 0x6000, address mask - 0xFF''' * SDB Device ID 0xf6a4e20c * [[DDR3 Stream FIFO CSR v1]]