FPGA Configuration Space (SDB)
This project defines data structures, to be embedded in the FPGA memory address space, to enumerate the devices that have been synthetized in the current design. The same structure is also used as a simple flash file system. AKA Self-Describing Bus (SDB) Specification for Logic Cores. The layout is simple enough to be parsed both by the host and by the internal soft-core, if any.
- AD5328 x2 SPI
- ADC CLK DIV Reset
- ADC Info
- ADC Pattern Test
- Board GPIO
- Calibration triggers
- CategorySDB
- Clock Control Registers
- Clock Control Registers v2.0
- Deserializers CSR
- FE-Link V2.0 CSR
- HWIP CSR 1.0
- HWIP_Error_Counters
- MCU Registers v1.0
- MCU Registers v2.0
- MPD TRC Core
- MSC Cycle counters CSR
- MSC Histograms CSR v1.0
- MSC Histograms CSR v2.0
- MSC Input CSR
- MSC Stream readout CSR v1.0
- MSC onboard CSR
- MSC16VE-EthRegisters_v2
- MStream Core 2.x
- MlinkCsr
- Network Port Registers
- Run Logic
- Run Statistic Module
- SDB
- SDB Devices
- SPI_NOR_Flash_Programmer
- Spill Control Module
- Statistics Readout Module v1.0
- TADC System Hit Core Registers
- TDC Core Registers TDC72 v1.0
- TDC Core Registers TQDC16VS v1.0
- TLU DesDec
- TLU TTL I/O Control
- TLU16SFP DesDec
- TLU16SFP Register Map
- TLU16SFP Trigger CSR
- TLU40LVDS Luminosity Trigger CSR
- TLU40LVDS Register Map
- TLU40LVDS TOF Trigger CSR
- TTVXS_Run_Control_Counters
- TrigInfo
- Trigger Control
- UT24VE TTL I/O Control
- WR Time Emulator
- WR_Status_Registers
- Waveform BLC
- Waveform Recorder Module
- Waveform Trig
- felink_v1_csr