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Size: 2431
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| Deletions are marked like this. | Additions are marked like this. |
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| ||<:>Address range||<:>Module || ||0x0040 - 0x005F ||[[#SYS_REG_CSR|CSR]]: [[TADC System CSR]] || ||0x0100 - 0x01FF ||[[#SYS_REG_TRG|Trigger control & statistic]]: [[TADC System Trigger CSR]] || ||0x0200 - 0x02FF ||[[#SYS_REG_TDC|TDC Core Registers]]: [[TADC System TDC Core Registers]] || ||0x0300 - 0x03FF ||[[#SYS_REG_ADC|ADC Core Registers]]: [[TADC System ADC Core Registers]] || ||0x0400 - 0x04FF ||[[#SYS_REG_WRE|WR Time Emulator Registers]] || ||0x0500 - 0x05FF ||[[#SYS_REG_DES|Deserializers]] || ||0x0600 - 0x06FF ||[[#SYS_REG_HIT|Input Hit Coutners]] || |
||<:>Address range||<:>Module || Registers Page || ||0x0040 - 0x005F ||[[#SYS_REG_CSR|CSR]] ||[[TADC System CSR]] || ||0x0100 - 0x01FF ||[[#SYS_REG_TRG|Trigger control & statistic]] ||[[TADC System Trigger CSR]] || ||0x0200 - 0x02FF ||[[#SYS_REG_TDC|TDC Core Registers]] ||[[TADC System TDC Core Registers]] || ||0x0300 - 0x03FF ||[[#SYS_REG_ADC|ADC Core Registers]] ||[[TADC System ADC Core Registers]] || ||0x0400 - 0x04FF ||[[#SYS_REG_WRE|WR Time Emulator Registers]] || || ||0x0500 - 0x05FF ||[[#SYS_REG_DES|Deserializers]] || || ||0x0600 - 0x06FF ||[[#SYS_REG_HIT|Input Hits Core ]] ||[[TADC System Hit Core Registers]] || |
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| Input Hit Counters | <<Include(TADC System Hit Core Registers)>> |
TDC and ADC System Registers
Intended to use with: TQDC16VS-E, TDC72VXS, TDC64VHLE-E, PHOS-FEC.
Registers are 16 bit width. 32-bit and 64-bit data is packed as following:
Reg # |
64-bit word |
0x70 |
bits 15:0 |
0x71 |
bits 31:16 |
0x72 |
bits 47:32 |
0x73 |
bits 63:48 |
Register I/O
System Registers, 0x0000 - 0x3FFF |
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Address range |
Module |
Registers Page |
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0x0040 - 0x005F |
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0x0100 - 0x01FF |
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0x0200 - 0x02FF |
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0x0300 - 0x03FF |
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0x0400 - 0x04FF |
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0x0500 - 0x05FF |
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0x0600 - 0x06FF |
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Board Level Registers, 0x4000 - 0x7FFF |
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Address range |
Module |
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0x4000 - 0x40FF |
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0x4100 - 0x41FF |
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0x4200 - 0x42FF |
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0x7000 - 0x70FF |
Flash programmator |
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System Registers
Base address - 0x0000, address mask - 0x3FFF.
CSR
Trigger control & statistic
TDC Core Registers
WR Time Emulator Registers
Deserializers control
TDC and ADC System - Hit Core Registers
SDB Device ID 0x2324ece4
Register Map
Base address - 0x0600, address mask - 0x00FF.
00h - Identification 2324ece4, 32 bits, RO
- 02h - reserved
03h - Counters lock, R/W
- [0] - counters lock
- [15:1] - reserved
04h - Counters Timestamp, 64 bits, RO
[63:0] - TAI 64-bit Timestamp
08h - Number of input hit channels, RO
- 09h~0Fh - reserved
10h - Comparators State, 128 bits, RO
18h - Trigger Edge Mask, 128 bits, R/W
bit# = channel#
Coding:
1 - Falling
0 - Rising
- 20h~7Fh - reserved
80h~9Eh - Hit Counters, 32 bits, RO
one channel per address
channel #0 in addr 80h~0x81h, channel #1 in addr 82h~83h, etc.
Board Level Registers
Base address - 0x4000, address mask - 0x3FFF.
MCU SPI Slave
SPI communication to ADCs
Thresholds setup