TDC and ADC System Registers

Intended to use with: TQDC16VS-E, TDC72VXS, TDC64VHLE-E, PHOS-FEC.

Registers are 16 bit width. 32-bit and 64-bit data is packed as following:

Reg #

64-bit word

0x70

bits 15:0

0x71

bits 31:16

0x72

bits 47:32

0x73

bits 63:48

Register I/O

System Registers, 0x0000 - 0x3FFF

Address range

Module

Registers Page

0x0040 - 0x005F

M-Link CSR

0x0060 - 0x007F

Run Control

TADC Run Logic

0x0100 - 0x01FF

Trigger control & statistic

Trigger Control Status Registers

0x0200 - 0x02FF

HPTDC JTAG Controller

HPTDC Controller Registers

0x0300 - 0x03FF

ADC Core Registers

TADC System ADC Core Registers

0x0400 - 0x04FF

WR Time Emulator Registers

0x0500 - 0x05FF

Deserializers

0x0600 - 0x06FF

Input Hits Core

TADC System Hit Core Registers

0x0700 - 0x07FF

Run Statistic

Run Statistic Module

0x0800 - 0x08FF

WhiteRabbit Status

WR Status Registers

0x0900 - 0x09FF

Statistics Readout

Statistics Readout Module

Board Level Registers, 0x4000 - 0x7FFF

Address range

Module

0x4000 - 0x40FF

MCU Registers v2.0

0x4100 - 0x41FF

SPI communication to ADCs

0x4200 - 0x42FF

Thresholds setup

0x7000 - 0x70FF

Flash Programmer

System Registers

Base address - 0x0000, address mask - 0x3FFF.

CSR

Trigger control & statistic

TDC Core Registers

WR Time Emulator Registers

Deserializers control

TDC and ADC System - Hit Core Registers

Register Map

Base address - 0x0600, address mask - 0x00FF.

  • 00h - Identification 2324ece4, 32 bits, RO

  • 02h - reserved

  • 03h - Counters lock, R/W

    • [0] - counters lock
    • [15:1] - reserved

  • 04h - Counters Timestamp, 64 bits, RO

  • 08h - Number of input hit channels, RO

  • 09h~0Fh - reserved

  • 10h - Comparators State, 128 bits, RO

  • 18h - Trigger Edge Mask, 128 bits, R/W

    • bit# = channel#

    • Coding:

      • 1 - Falling

      • 0 - Rising

  • 20h~7Fh - reserved

  • 80h~9Eh - Hit Counters, 32 bits, RO

    • one channel per address

    • channel #0 in addr 80h~0x81h, channel #1 in addr 82h~83h, etc.

SDB

Board Level Registers

Base address - 0x4000, address mask - 0x3FFF.

SPI communication to ADCs

Thresholds setup

MLinkRegisters

TADC_System_Registers (last edited 2022-08-22 08:08:07 by sav)