• UT24VE-TRC-Registers

UT24VE-TRC module registers v1

Hardware UT24VE

Module: UT24VE-TRC

Registers are 16 bit width. 32-bit and 64-bit data is packed as following:

Register I/O

PHY TRIG System registers

Base address - 0x1000, address mask - 0x0FFF.

Core registers

Base address - 0x0000, address mask - 0x001F.

• 0x00 - Control (16 bits), R/W
  • [0] - Softclear
  • [1] - Counters lock
  • [2] - Memory input data (0 - raw data, 1 - out_d_triggers)
  • [3] - Accept trigger (0 - any trig in match window, 1 - lut output)
  • [4] - L0 extend disable (0 - L0 gate, 1 - L0 pulse)
• 0x01 - Number of channels (16 bits), RO
  • [7:0] - PHY channels

  • [15:8] - AUX channels

• 0x02 - match_window (16 bits), R/W
• 0x03 - trig_delay (16 bits), R/W
• 0x06 - ch_en (32 bits), R/W
• 0x08 - start_channel_mask (32 bits), R/W
• 0x0A - Period of a periodic timer in clocks (32 bits), R/W
• 0x0C - Period of a random timer in clocks (32 bits), R/W
• 0x0E - Dead time for trigger in clocks (32 bits), R/W
• 0x10 - Calibration trigger offset from spill le in clocks (32 bits), R/W

• 0x12 - Calibration trigger period (32 bits), R/W

• 0x14 - Calibration trigger number (16 bits), R/W
• 0x15 - L0 extend time (additional time after L1) in clocks (16 bits), R/W
• 0x16 - read_channel_mask (32 bits), R/W

Channel registers

Base address - 0x0200, address mask - 0x007F.

• 0x00 - 64-bit register for ch #0, R/W
• [0] - before protection enabled
• [1] - after protection enabled
• [2] - reduction enabled
• [11:4] - channel delay in clocks
• [31:16] - reduction factor
• [47:32] - before protection time in clocks
• [63:48] - after protection time in clocks
• 0x04 - 64-bit register for ch #1, R/W
• 0x08 - 64-bit register for ch #2, R/W

......

• 0x7C - 64-bit register for ch #31, R/W

Event memory

Base address - 0x0500, address mask - 0x000F.

• 0x0 - lattency (16 bits), R/W
• 0x1 - read points (16 bits), R/W
• 0x3 - Control (16 bits), R/W (v2.0+)
  • [0] - Channel oscilogram enable

Input Hit Coutners after delay

Base address - 0x0600, address mask - 0x01FF.

xOff = from the end of Match Win till L1

Defenition of each section is the same as in U40VE-RC module registers v2.0 (Counters registers)

before/after fail counters

Base address - 0x0800, address mask - 0x01FF.

Input Hit Coutners after reduction

Base address - 0x0A00, address mask - 0x01FF.

xOff = from the end of Match Win till L1

Defenition of each section is the same as in U40VE-RC module registers v2.0 (Counters registers)

Event Readout Controller

• 0x00 - Control (16 bits), R/W
  • [1] - Counters lock
  • [2] - Channel oscilogram enable
• 0x4 - Set next Global Even number (64 bits), R/W
• 0x8 - Set next Global Even number (64 bits), R/W

MLinkRegisters UT24VE