#<> = UT24VE-TRC module registers v1 = Hardware [[UT24VE]] Module: [[UT24VE_TRC|UT24VE-TRC]] Registers are 16 bit width. 32-bit and 64-bit data is packed as following: ||Reg # ||64-bit word || ||0x70 ||bits 15:0 || ||0x71 ||bits 31:16 || ||0x72 ||bits 47:32 || ||0x73 ||bits 63:48 || == Register I/O == ||<-32 rowclass="bits">Top level, 0x0000 - 0x7FFF || ||<:>Address range||<:>Module || ||0x0040 - 0x005F ||[[MlinkCsr|M-Link CSR]] || ||0x1000 - 0x1FFF ||[[#SYS_REGS|PHY TRIG System registers]] || ||0x2000 - 0x200F ||[[#ERC_REG|Event Readout Controller]] || ||0x3000 - 0x301F ||[[WR_Status_Registers|White Rabbit Status Registers]]|| ||0x7000 - 0x70FF ||[[SPI_NOR_Flash_Programmer]] (SDB) || ||0x7C00 - 0x7FFF ||[[SdbDevices|SDB]] || ---- <> == PHY TRIG System registers == '''Base address - 0x1000, address mask - 0x0FFF.''' ||<-32 rowclass="bits">PHY TRIG System registers, 0x0000 - 0x0FFF || ||<:>Address range||<:>Module || ||0x0000 - 0x001F ||[[#SYS_REG_CORE|Core registers]] || ||0x0200 - 0x027F ||[[#SYS_REG_CH|Channel registers]] || ||0x0300 - 0x033F ||[[Spill Control Module]] (SDB) || ||0x0500 - 0x050F ||[[#SYS_REG_EVENT_MEM|Event memory]] || ||0x0600 - 0x07FF ||[[#SYS_REG_HIT_D|Input Hit Coutners after delay]] || ||0x0800 - 0x09FF ||[[#SYS_REG_BA_FAIL_CNT|before/after fail counters]] || ||0x0A00 - 0x0BFF ||[[#SYS_REG_HIT_R|Input Hit Coutners after reduction]]|| ---- <> === Core registers === '''Base address - 0x0000, address mask - 0x001F.''' * 0x00 - Control (16 bits), R/W . [0] - Softclear . [1] - Counters lock . [2] - Memory input data (0 - raw data, 1 - out_d_triggers) . [3] - Accept trigger (0 - any trig in match window, 1 - lut output) . [4] - L0 extend disable (0 - L0 gate, 1 - L0 pulse) * 0x01 - Number of channels (16 bits), RO . [7:0] - PHY channels . [15:8] - [[UT24VE-TRC-AUX-Сhannels|AUX channels]] * 0x02 - match_window (16 bits), R/W * 0x03 - trig_delay (16 bits), R/W * 0x06 - ch_en (32 bits), R/W * 0x08 - start_channel_mask (32 bits), R/W * 0x0A - Period of a periodic timer in clocks (32 bits), R/W * 0x0C - Period of a random timer in clocks (32 bits), R/W * 0x0E - Dead time for trigger in clocks (32 bits), R/W * 0x10 - Calibration trigger offset from spill le in clocks (32 bits), R/W * 0x12 - [[UT24VE-TRC-AUX-Сhannels|Calibration trigger]] period (32 bits), R/W * 0x14 - Calibration trigger number (16 bits), R/W * 0x15 - L0 extend time (additional time after L1) in clocks (16 bits), R/W * 0x16 - read_channel_mask (32 bits), R/W ---- <> === Channel registers === '''Base address - 0x0200, address mask - 0x007F.''' * 0x00 - 64-bit register for ch #0, R/W . [0] - before protection enabled . [1] - after protection enabled . [2] - reduction enabled . [11:4] - channel delay in clocks . [31:16] - reduction factor . [47:32] - before protection time in clocks . [63:48] - after protection time in clocks * 0x04 - 64-bit register for ch #1, R/W * 0x08 - 64-bit register for ch #2, R/W ...... * 0x7C - 64-bit register for ch #31, R/W ---- <> === Event memory === '''Base address - 0x0500, address mask - 0x000F.''' * 0x0 - lattency (16 bits), R/W * 0x1 - read points (16 bits), R/W ---- <> === Input Hit Coutners after delay === '''Base address - 0x0600, address mask - 0x01FF.''' ||'''address'''||''' Hit up conditions'''|| ||0x000-0x03F||xOff|| ||0x040-0x07F||~xOff|| ||0x080-0x0BF||xOff & Run|| ||0x0C0-0x0FF||~xOff & Run|| ||0x100-0x13F||xOff & Spill|| ||0x140-0x17F||~xOff & Spill|| ||0x180-0x1BF||xOff & Run & Spill|| ||0x1C0-0x1FF||~xOff & Run & Spill|| xOff = from the end of Match Win till L1 Defenition of each section is the same as in U40VE-RC module registers v2.0 ([[U40VE-RC-Registers#SYS_REG_COUNTERS|Counters registers]]) ---- <> === before/after fail counters === '''Base address - 0x0800, address mask - 0x01FF.''' ||'''address'''||'''Description'''|| ||0x000-0x03F||Before error Counters|| ||0x040-0x07F||After error Counters|| ---- <> === Input Hit Coutners after reduction === '''Base address - 0x0A00, address mask - 0x01FF.''' ||'''address'''||''' Hit up conditions'''|| ||0x000-0x03F||xOff|| ||0x040-0x07F||~xOff|| ||0x080-0x0BF||xOff & Run|| ||0x0C0-0x0FF||~xOff & Run|| ||0x100-0x13F||xOff & Spill|| ||0x140-0x17F||~xOff & Spill|| ||0x180-0x1BF||xOff & Run & Spill|| ||0x1C0-0x1FF||~xOff & Run & Spill|| xOff = from the end of Match Win till L1 Defenition of each section is the same as in U40VE-RC module registers v2.0 ([[U40VE-RC-Registers#SYS_REG_COUNTERS|Counters registers]]) ---- <> == Event Readout Controller == * 0x00 - Control (16 bits), R/W . [1] - Counters lock . [2] - Channel oscilogram enable * 0x4 - Set next Global Even number (64 bits), R/W * 0x8 - Set next Global Even number (64 bits), R/W ------ [[CategoryMlinkRegisters|MLinkRegisters]]