• PHOS FEC Register Map

PHOS FEC Register Map

Hardware: PHOS FEC

Registers are 16 bit width. 32-bit and 64-bit data is packed as following:

Register I/O

System Registers

Base address - 0x0000, address mask - 0x3FFF.

Board Level Registers

Base address - 0x4000, address mask - 0x0FFF.

Deserializers control

Base address - 0x4000, address mask - 0x00FF.

Reg 0, @0x0000 - Deserializer control, R/W

• [15] - ADC Reset
• [14] - Deserializers Reset
• [13] - Status Reset
• [12] - Reset (ADS52J90 SYNC pin)

Reg 1, @0x0001 - Deserializer status, RO

• [0] - deserializer #0 lock status
• [1] - deserializer #0 unlocked (but previously was locked)
• [2] - deserializer #1 lock status
• [3] - deserializer #1 unlocked (but previously was locked)
• [15:4] - reserved

Reg 2, @0x0002 - reserved

Reg 3, @0x0003 - IDELAY Tap Value, R/W

Reg 4, @0x0004 - IDELAY Load Mask, R/W

Reg 5, @0x0005 - ADC and Channel number info RO

• [7:0] - number of ADC chips
• [15:8] - number of channels per ADC chip

Base address - 0x4100, address mask - 0x00FF.

Device: 2x ADS52J90

Reg 0, @0x0000 - set SPI address, R/W

Reg 1, @0x0001 - set SPI write data, R/W

Reg 2, @0x0002 - SPI read data form ADC, RO

Reg 3, @0x0003 - unused, R/W

Reg 4, @0x0004 - active ADC select, R/W

• valid values are:
• - 0x1 for ADC #0
• - 0x2 for ADC #1

HV setup

Base address - 0x4200, address mask - 0x00FF.

Device: 4x AD5328

Reg 0, @0x0000, Thresholds setup for channels 0..7, R/W

• [15:0] - DAC data

Reg 1, @0x0001, Thresholds setup for channels 15..8, R/W

• [15:0] - DAC data

Reg 2, @0x0002, Thresholds setup for channels 23..16, R/W

• [15:0] - DAC data

Reg 3, @0x0003, Thresholds setup for channels 31..24, R/W

• [15:0] - DAC data

Thresholds setup

Base address - 0x4300, address mask - 0x00FF.

Device: 4x AD5328

Reg 0, @0x0000, Thresholds setup for channels 0..7, R/W

• [15:0] - DAC data

Reg 1, @0x0001, Thresholds setup for channels 15..8, R/W

• [15:0] - DAC data

Reg 2, @0x0002, Thresholds setup for channels 23..16, R/W

• [15:0] - DAC data

Reg 3, @0x0003, Thresholds setup for channels 31..24, R/W

• [15:0] - DAC data

PLL Management

Base address - 0x4400, address mask - 0x00FF.

Device: SI5326

Reg 0-127, @0x0000-0x007F, PLL SPI Commands (configuration sequence), R/W

• [7:0] - SPI write data
• [15:8] - SPI write address

Reg 128, @0x0080, PLL management FSM Control, R/W

• [0] - PLL reconfig request (start SPI sequence)
• [1] - request to communicate with configuration RAM
• [15:2] - reserved

Reg 129, @0x0081, FSM state, RO

• [0] - Init
• [1] - Idle
• [2] - software RAM read/write
• [3] - read command from RAM into SPI PHY
• [4] - SPI PHY address write
• [5] - SPI PHY data write
• [15:6] - reserved

Reg 130, @0x0082, Number of SPI commands in RAM, R/W

Reg 131, @0x0083, PLL Status, RO

• [0] - PLL LOL pin
• [1] - PLL INT_C1B pin
• [2] - PLL C2B pin
• [15:3] - reserved

MLinkRegisters