#<> = PHOS FEC Register Map = Hardware: [[PHOS FEC]] Registers are 16 bit width. 32-bit and 64-bit data is packed as following: ||Reg # ||64-bit word || ||0x70 ||bits 15:0 || ||0x71 ||bits 31:16 || ||0x72 ||bits 47:32 || ||0x73 ||bits 63:48 || == Register I/O == ||<-32 rowclass="bits">[[#SYS_REGS|System Registers]], 0x0000 - 0x3FFF|| ||<:>Address range||<:>Module || ||0x0040 - 0x005F ||[[TADC CSR|Module CSR]] || ||0x0060 - 0x007F ||[[TADC Run Logic Registers|Run Logic]] || ||0x0100 - 0x01FF ||[[TADC Trigger Registers|Trigger control & statistic]]|| ||0x0200 - 0x02FF ||[[TADC TDC Core Registers|TDC Core Registers]] || ||0x0300 - 0x03FF ||[[TADC ADC Core Registers|ADC Core Registers]] || ||0x0400 - 0x04FF ||[[#SYS_REG_WRE|WR Time Emulator Registers]] || ||0x0500 - 0x05FF ||reserved || ||0x0600 - 0x06FF ||[[TADC Hit Core Registers|Hit Core Registers]] || ||0x0700 - 0x07FF ||[[TADC Run Statistic Counters|Run Statistic Counters]]|| ||0x0800 - 0x08FF ||reserved (White Rabbit Status Registers) || ||0x0900 - 0x09FF ||[[TADC Statistics Readout CSR|Statistics Readout CSR]]|| ||0x1000 - 0x3FFF ||reserved|| ||<-32 rowclass="bits">[[#BOARD_REGS|Board Level Registers]], 0x4000 - 0x7FFF|| ||<:>'''Address range'''||<:>'''Module'''|| ||0x4000 - 0x40FF ||[[#BRD_REG_DES|Deserializers Control & Status]]|| ||0x4100 - 0x41FF ||[[#BRD_ADC_SPI|SPI communication to ADCs]] || ||0x4200 - 0x42FF ||[[#BRD_DAC_HV|HV setup]]|| ||0x4300 - 0x43FF ||[[#BRD_DAC_THR|Thresholds setup]]|| ||0x4400 - 0x44FF ||[[#BRD_PLL_MGMT|PLL management]]|| ||0x4500 - 0x45FF ||reserved (DigiPOT management)|| ||0x7000 - 0x70FF ||[[SPI_NOR_Flash_Programmer|Flash Programmer]]|| ||0x7C00 - 0x7FFF ||reserved ([[CategorySDB|SDB]])|| ---- ---- <> == System Registers == '''Base address - 0x0000, address mask - 0x3FFF.''' ---- ---- <> == Board Level Registers == '''Base address - 0x4000, address mask - 0x0FFF.''' ---- <> === Deserializers control === '''Base address - 0x4000, address mask - 0x00FF.''' Reg 0, @0x0000 - Deserializer control, R/W . [15] - ADC Reset . [14] - Deserializers Reset . [13] - Status Reset . [12] - Reset (ADS52J90 SYNC pin) Reg 1, @0x0001 - Deserializer status, RO . [0] - deserializer #0 lock status . [1] - deserializer #0 unlocked (but previously was locked) . [2] - deserializer #1 lock status . [3] - deserializer #1 unlocked (but previously was locked) . [15:4] - reserved Reg 2, @0x0002 - reserved Reg 3, @0x0003 - IDELAY Tap Value, R/W Reg 4, @0x0004 - IDELAY Load Mask, R/W Reg 5, @0x0005 - ADC and Channel number info RO . [7:0] - number of ADC chips . [15:8] - number of channels per ADC chip ---- <> '''Base address - 0x4100, address mask - 0x00FF.''' ''Device: 2x ADS52J90'' Reg 0, @0x0000 - set SPI address, R/W Reg 1, @0x0001 - set SPI write data, R/W Reg 2, @0x0002 - SPI read data form ADC, RO Reg 3, @0x0003 - unused, R/W Reg 4, @0x0004 - active ADC select, R/W . valid values are: .- 0x1 for ADC #0 .- 0x2 for ADC #1 ---- <> === HV setup === '''Base address - 0x4200, address mask - 0x00FF.''' ''Device: 4x AD5328'' Reg 0, @0x0000, Thresholds setup for channels 0..7, R/W . [15:0] - DAC data Reg 1, @0x0001, Thresholds setup for channels 15..8, R/W . [15:0] - DAC data Reg 2, @0x0002, Thresholds setup for channels 23..16, R/W . [15:0] - DAC data Reg 3, @0x0003, Thresholds setup for channels 31..24, R/W . [15:0] - DAC data ---- <> === Thresholds setup === '''Base address - 0x4300, address mask - 0x00FF.''' ''Device: 4x AD5328'' Reg 0, @0x0000, Thresholds setup for channels 0..7, R/W . [15:0] - DAC data Reg 1, @0x0001, Thresholds setup for channels 15..8, R/W . [15:0] - DAC data Reg 2, @0x0002, Thresholds setup for channels 23..16, R/W . [15:0] - DAC data Reg 3, @0x0003, Thresholds setup for channels 31..24, R/W . [15:0] - DAC data ---- <> === PLL Management === '''Base address - 0x4400, address mask - 0x00FF.''' ''Device: SI5326'' Reg 0-127, @0x0000-0x007F, PLL SPI Commands (configuration sequence), R/W . [7:0] - SPI write data . [15:8] - SPI write address Reg 128, @0x0080, PLL management FSM Control, R/W . [0] - PLL reconfig request (start SPI sequence) . [1] - request to communicate with configuration RAM . [15:2] - reserved Reg 129, @0x0081, FSM state, RO . [0] - Init . [1] - Idle . [2] - software RAM read/write . [3] - read command from RAM into SPI PHY . [4] - SPI PHY address write . [5] - SPI PHY data write . [15:6] - reserved Reg 130, @0x0082, Number of SPI commands in RAM, R/W Reg 131, @0x0083, PLL Status, RO . [0] - PLL LOL pin . [1] - PLL INT_C1B pin . [2] - PLL C2B pin . [15:3] - reserved ---- ---- [[CategoryMlinkRegisters|MLinkRegisters]]