PCI Digitizer, VME TDC, PCI VME Master, Data Acquisition System

DataFormatTQDC

Last updated at 2017-02-13 13:42:02

TQDC Raw Data Format

Hardware: TQDC-16 TQDC16VS

See also: VME DAQ Rawdata Format LTM9011-14 datasheet

Data types
0	input counters high bits
1	input counters low bits
2	TDC header
3	TDC trailer
4	ADC timestamp or TDC data
5	TDC or ADC data
6	TDC error
7

ADC clock is:

12.5 ns for old systems
12 ns for new systems
8 ns for TQDC16VS

TDC clock is:

25 ns for old systems
24 ns for new systems

0 - input counters high bits
31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
0				channel									0	0	0	counter bits 31:16

1 - input counters low bits
31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
1				channel									0	0	0	counter bits 15:0

Number of adc hits in past burst. If channel=0x1FF than counter bits - is time of last burst, else channel should be masked with 0x1F

2 - TDC event header
31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
2				0		reserved		event number												TDC timestamp

TDC timestamp in number of TDC clocks since global trigger timestamp found in event header.

3 - TDC event trailer
31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
3				0		reserved		event number												TDC word count

4, mode!=0 - ADC timestamp, word 1
31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
4				mode		reserved		channel					0	0	0	Trigger timestamp

Trigger timestamp in number of ADC clocks since start of spill.

4, mode!=0 - ADC timestamp, word 2
31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
4				mode		reserved		channel					0	0	1	ADC timestamp

ADC timestamp in number of ADC clock since start of spill.

4, mode=0 - TDC data
31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
4				mode=0		rcdata		channel					data

5 - TDC and ADC data, select by mode field
31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
5				mode		rcdata		channel					data

Channels 16-31 are reserved.

Mode 0 - TDC time measurement

data bits 18:0 = number of 100 ps time intervals since global trigger timestamp found in event header. When 25 ps mode is active, use rcdata[1:0] for 2 LSB bits of time measurement.

Mode 1 - calibration

data bits 15:0 = adc sample.
data bits 18:16 - reserved

Mode 2 - ADC sampling

data bits 15:0 = adc sample.
data bits 18:16 - reserved

Mode 3 - ADC integration

data bits 18:0 - sum of adc samples

ADC is sampling at 100 MHz with resolution of 10 bits.

6 - TDC error
31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
6				reserved													TDC error flags

TDC error flags bits:

[0] Hit lost in group 0 from read-out fifo overflow
[1] Hit lost in group 0 from L1 buffer overflow
[2] Hit error have been detected in group 0
[3] Hit lost in group 1 from read-out fifo overflow
[4] Hit lost in group 1 from L1 buffer overflow
[5] Hit error have been detected in group 1
[6] Hit lost in group 2 from read-out fifo overflow
[7] Hit lost in group 2 from L1 buffer overflow
[8] Hit error have been detected in group 2
[9] Hit lost in group 3 from read-out fifo overflow
[10] Hit lost in group 3 from L1 buffer overflow
[11] Hit error have been detected in group 3
[12] Hits rejected because of programmed event size limit
[13] Event lost (trigger FIFO ovefrlow)
[14] Internal fatal chip error has been detected

Most important error bits are 12 and 13. Error bit 14 should be ignored.

For detailed description of TDC please refer to HPTDC manual.

DataFormatTQDC (last edited 2017-02-13 13:42:02 by filippov)