• Clock Control Registers v2.0

Clock Control Registers v2.0

• SDB Device ID 0x7bc301a9

• Clock Control Registers

Register Map

address space 0x000 - 0xFF

• 00h - Identification 7bc301a9, 32 bits, RO static

• 02h - reserved

• 03h - reserved

• 04h - PLL bypass, R/W

  • [0] - '1' - bypass (default), '0' - clock via PLL

• 05h - Clock Control, R/W

  • [15] - automatic (default)
  • [3] - REF 10 MHz
  • [2] - VXS backplane
  • [1] - REF 41.6(6) MHz
  • [0] - Local

• 06h - Clock Status, '1' - clock ok, RO

  • [3] - REF 10 MHz
  • [2] - VXS backplane
  • [1] - REF 41.6(6) MHz
  • [0] - Local

• 07h - System Clock Source, RO

  • [15] - PLL bypassed
  • [3] - REF 10 MHz
  • [2] - VXS backplane
  • [1] - REF 41.6(6) MHz
  • [0] - Local

• 08h - Clock Source Control Capability, RO static

  • [15] - automatic
  • [3] - REF 10 MHz
  • [2] - VXS backplane
  • [1] - REF 41.6(6) MHz
  • [0] - Local

SDB