• Clock Control Registers

Clock Control Registers v1.0

• SDB Device ID 0x7bc301a9

• Clock Control Registers v2.0

Register Map

address space 0x00 - 0x0F

Reg 0x0000 - Clock Control, R/W

• [15:1] - reserved
• [0] - on-board PLL bypass: '1' - bypass (default), '0' - clock via PLL

Reg 0x0001 - Clock Status, RO

• [15:3] - reserved
• [2] - VXS clock status ('1' - clock ok)
• [1] - TTC clock status ('1' - clock ok)
• [0] - Logic 1

Reg 0x0002 - System Clock Source, RO

• [15:3] - reserved
• [2] - VXS (highest priority)
• [1] - TTC
• [0] - On-Board Oscillator (lowest priority)

SDB