Contents
MSC16VE-E module registers
Hardware: MSC16VE
Registers are 16 bit width. 32-bit and 64-bit data is packed as following:
Reg # |
64-bit word |
0x70 |
bits 15:0 |
0x71 |
bits 31:16 |
0x72 |
bits 47:32 |
0x73 |
bits 63:48 |
Register I/O
address |
Description |
0x40-0x5F |
|
0x60-0x7F |
|
0x80-0xBF |
|
0x200-0x201 |
|
0x200-0x3FF |
|
0xA00-0xA3F |
0x40-0x5F — CSR
Reg 0x40, CTRL, R/W
- [0] - softclear (clear statistics)
- [1] - counters lock (0 - counters enable, 1 - lock)
- [2] - enable Hamming code error count
- [15:3] - reserved
Reg 0x42, DEVICE_ID, RO
[15:8] - device id
- [7:0] - reserved (0)
Reg 0x43, Live Magic, R/W
- [15:0] - data
Reg 0x50, SERIAL_ID, 64-bit Board Serial Number (DS18B20), RO
Reg 0x54, TEMPERATURE, current temperature, RO
Reg 0x55, reserved, RO
Reg 0x56, FW_VER, 16-bit, firmware version number, RO
Reg 0x57, FW_REV, 16-bit, firmware revision number, RO
0x80-0xBF — MSC16VE Scaler Setup
Reg 0x81, write to ram/current ram address cnt, start-1/stop-0 , R/W (NOT USED)
Reg 0x82, Channel grouping, R/W
- [0] - when set: 16 channels, 7-bit counter per channel
- [1] - when set: 8 channels, 14-bit counter per channel
- [2] - when set: 4 channels, 28-bit counter per channel
- [15:3] - reserved
Reg 0x84, compstate , RO
Reg 0x85, spill state, RO
Reg 0x86-0x87, steptimer, 32-bits, R/W
Reg 0x92-0x93, spillplot step value (clk), 32-bits, R/W
Reg 0x94-0x95, spillplot current ram address, 32-bits, RO
Reg 0x96-0x97, spillplot offset (clk), 32-bits, R/W
Reg 0xA0-0xA3 msc start timestamp, RO
Spill registers
Reg 0x90-0x91, spill counter, RO
Reg 0xA4-0xA7, spill timestamp, RO
0x200 - 0x201 — DAC treshold
Reg 0x200, Threshold DAC , R/W
Reg 0x201, Threshold DAC , R/W
Histograms setup
Base address - 0x0300, address mask - 0x00FF.
Reg 0x300, Histogram step, channel #1, 32-bit, R/w
Reg 0x302, Histogram step, channel #2, 32-bit, R/w
Reg 0x304, Histogram step, channel #3, 32-bit, R/w
Reg 0x306, Histogram step, channel #4, 32-bit, R/w
Reg 0x308, Histogram step, channel #5, 32-bit, R/w
Reg 0x30A, Histogram step, channel #6, 32-bit, R/w
Reg 0x30C, Histogram step, channel #7, 32-bit, R/w
Reg 0x30E, Histogram step, channel #8, 32-bit, R/w
Reg 0x310, Histogram step, channel #9, 32-bit, R/w
Reg 0x312, Histogram step, channel #10, 32-bit, R/w
Reg 0x314, Histogram step, channel #11, 32-bit, R/w
Reg 0x316, Histogram step, channel #12, 32-bit, R/w
Reg 0x318, Histogram step, channel #13, 32-bit, R/w
Reg 0x31A, Histogram step, channel #14, 32-bit, R/w
Reg 0x31C, Histogram step, channel #15, 32-bit, R/w
Reg 0x31E, Histogram step, channel #16, 32-bit, R/w
Regs 0x320-0x3FF - reserved
Hits for Spill & Cycle Counters
Base address - 0x0A00, address mask - 0x003F.
Reg 0xA00, Hits for spill counter, channel #1, 32-bit, RO
Reg 0xA02, Hits for spill counter, channel #2, 32-bit, RO
Reg 0xA04, Hits for spill counter, channel #3, 32-bit, RO
Reg 0xA06, Hits for spill counter, channel #4, 32-bit, RO
Reg 0xA08, Hits for spill counter, channel #5, 32-bit, RO
Reg 0xA0A, Hits for spill counter, channel #6, 32-bit, RO
Reg 0xA0C, Hits for spill counter, channel #7, 32-bit, RO
Reg 0xA0E, Hits for spill counter, channel #8, 32-bit, RO
Reg 0xA10, Hits for spill counter, channel #9, 32-bit, RO
Reg 0xA12, Hits for spill counter, channel #10, 32-bit, RO
Reg 0xA14, Hits for spill counter, channel #11, 32-bit, RO
Reg 0xA16, Hits for spill counter, channel #12, 32-bit, RO
Reg 0xA18, Hits for spill counter, channel #13, 32-bit, RO
Reg 0xA1A, Hits for spill counter, channel #14, 32-bit, RO
Reg 0xA1C, Hits for spill counter, channel #15, 32-bit, RO
Reg 0xA1E, Hits for spill counter, channel #16, 32-bit, RO
Reg 0xA20, Hits for cycle counter, channel #1, 32-bit, RO
Reg 0xA22, Hits for cycle counter, channel #2, 32-bit, RO
Reg 0xA24, Hits for cycle counter, channel #3, 32-bit, RO
Reg 0xA26, Hits for cycle counter, channel #4, 32-bit, RO
Reg 0xA28, Hits for cycle counter, channel #5, 32-bit, RO
Reg 0xA2A, Hits for cycle counter, channel #6, 32-bit, RO
Reg 0xA2C, Hits for cycle counter, channel #7, 32-bit, RO
Reg 0xA2E, Hits for cycle counter, channel #8, 32-bit, RO
Reg 0xA30, Hits for cycle counter, channel #9, 32-bit, RO
Reg 0xA32, Hits for cycle counter, channel #10, 32-bit, RO
Reg 0xA34, Hits for cycle counter, channel #11, 32-bit, RO
Reg 0xA36, Hits for cycle counter, channel #12, 32-bit, RO
Reg 0xA38, Hits for cycle counter, channel #13, 32-bit, RO
Reg 0xA3A, Hits for cycle counter, channel #14, 32-bit, RO
Reg 0xA3C, Hits for cycle counter, channel #15, 32-bit, RO
Reg 0xA3E, Hits for cycle counter, channel #16, 32-bit, RO
Memory I/O FOR MSC16VE_HWIP_TEST only
word address |
Description |
0x000000-0x001FFF |
Plot RAM CH1 |
0x002000-0x003FFF |
Plot RAM CH2 |
0x004000-0x005FFF |
Plot RAM CH3 |
.... |
............ |
0x00E000-0x00FFFF |
Plot RAM CH8 |
0x010000-0x011FFF |
Plot RAM CH9 |
.... |
............ |
0x01E000-0x01FFFF |
Plot RAM CH16 |