• U40VE-RC-Registers_v1

U40VE-RC module registers v1.0

Hardware: U40VE-RC

Registers are 16 bit width. 32-bit and 64-bit data is packed as following:

Register I/O

M-Link CSR

Reg 0x40, CTRL, R/W

• [0] - softclear (clear statistics)
• [1] - counters lock (0 - counters enable, 1 - lock)
• [15:2] - reserved

Reg 0x42, DEVICE_ID, RO

• [15:8] - device id

• [7:0] - reserved (0)

Reg 0x43, Live Magic, R/W

• [15:0] - data

Reg 0x4F, MSTREAM_CFG, 16-bit MStream configuration, RO

Reg 0x50, SERIAL_ID, 64-bit Board Serial Number (DS18B20), RO

Reg 0x54, TEMPERATURE, current temperature, RO

Reg 0x55, reserved, RO

Reg 0x56, FW_VER, 16-bit, firmware version number, RO

Reg 0x57, FW_REV, 16-bit, firmware revision number, RO

Run Control Core

Reg 0x080 - 0x09F, Run Control Core Registers

Reg 0x080, rc_ctrl, R/W

• [0] - clear
• [13:1] - reserved (0)
• [14] - soft spill enable (default disable 0)
• [15] - run enable (default 1)

Reg 0x081, channel count, RO

Reg 0x082, trigger source select, R/W

• [0] - LEMO input
• [13:1] - reserved
• [14] - random pulser
• [15] - fixed frequency pulser

Reg 0x083, trigger state, RO

Reg 0x084, xoff input mask, R/W

Reg 0x085, xoff input state, RO

Reg 0x086, trigger output mask, R/W

Reg 0x087, xoff timeout state, RO

Reg 0x088-0x089, fixed frequency pulser period, R/W

Reg 0x08A-0x08B, random pulser probability, R/W

Reg 0x08C, spill start offset ms, R/W

Reg 0x08D, spill duration ms, R/W

Reg 0x08E, spill deny(interspill) ms, R/W

Reg 0x090, soft spill pause ms, R/W

Reg 0x091, soft spill width ms, R/W

Counters

Reg 0x100 - 0x13F, 16 x 64-bit level sensitive counters, RO

Reg 0x200 - 0x21F, 16 x 32-bit edge sensitive counters, RO

MLinkRegisters