= U40VE-RC module registers v1.0 =

Hardware: [[U40VE-RC]]

Registers are 16 bit width. 32-bit and 64-bit data is packed as following:
||Reg #||64-bit word||
||0x70||bits 15:0||
||0x71||bits 31:16||
||0x72||bits 47:32||
||0x73||bits 63:48||

== Register I/O ==

||address||Module||
||0x040 - 0x05F||[[MlinkCsr|M-Link CSR]]||
||0x100 - 0x0FF||Counters||

||address||Description||
||0x40||[[#REGCONTROL|Control]]||
||0x41||[[#REGSTATUS|Status]]||
||0x42||[[#REGDEVICEID|Device ID]]||
||0x43||[[#REGTEST|LiveMagic]]||
||0x44-0x4E|| ||
||0x4F||[[#REG_MSTREAM_CFG|MStream cfg]]||
||0x50-0x53||[[#REGSERIALID|64-bit Serial ID]]||
||0x54||[[#REGTEMPERATURE|Temperature]]||
||0x55|| ||
||0x56||[[#REGFWVER|Firmware Version]]||
||0x57||[[#REGFWREV|Firmware Revision]]||
||0x58-0x5F|| ||
||0x60-0x7F|| ||
||0x80-0xFF||Run Control Registers ||
||0x100-0x13F||Level Counters||
||0x200-0x21F||Edge Counters||

<<Anchor(REGCONTROL)>>

== M-Link CSR ==

Reg 0x40, CTRL, R/W
 . [0] - softclear (clear statistics)
 . [1] - counters lock (0 - counters enable, 1 - lock)
 . [15:2] - reserved

<<Anchor(REGDEVICEID)>>
Reg 0x42, DEVICE_ID, RO
 . [15:8] - [[DeviceId|device id]]
 . [7:0] - reserved (0)

<<Anchor(REG_TEST)>>
Reg 0x43, Live Magic, R/W
 . [15:0] - data

<<Anchor(REG_MSTREAM_CFG)>>
Reg 0x4F, MSTREAM_CFG, 16-bit MStream configuration, RO

<<Anchor(REG_SERIAL_ID)>>
Reg 0x50, SERIAL_ID, 64-bit Board Serial Number (DS18B20), RO

<<Anchor(REG_TEMPERATURE)>>
Reg 0x54, TEMPERATURE, current temperature, RO

Reg 0x55, reserved, RO

<<Anchor(REG_FW_VER)>>
Reg 0x56, FW_VER, 16-bit, firmware version number, RO

<<Anchor(REG_FW_REV)>>
Reg 0x57, FW_REV, 16-bit, firmware revision number, RO

== Run Control Core ==

<<Anchor(REG_RC_CORE)>>

Reg 0x080 - 0x09F, Run Control Core Registers

Reg 0x080, rc_ctrl, R/W
 . [0] - clear
 . [13:1] - reserved (0)
 . [14] - soft spill enable (default disable 0)
 . [15] - run enable (default 1)

Reg 0x081, channel count, RO

Reg 0x082, trigger source select, R/W
 . [0] - LEMO input
 . [13:1] - reserved
 . [14] - random pulser
 . [15] - fixed frequency pulser

Reg 0x083, trigger state, RO

Reg 0x084, xoff input mask, R/W

Reg 0x085, xoff input state, RO

Reg 0x086, trigger output mask, R/W

Reg 0x087, xoff timeout state, RO

Reg 0x088-0x089, fixed frequency pulser period, R/W

Reg 0x08A-0x08B, random pulser probability, R/W

Reg 0x08C, spill start offset ms, R/W

Reg 0x08D, spill duration ms, R/W

Reg 0x08E, spill deny(interspill) ms, R/W

Reg 0x090, soft spill pause ms, R/W

Reg 0x091, soft spill width ms, R/W

== Counters ==

Reg 0x100 - 0x13F, 16 x 64-bit level sensitive counters, RO

Reg 0x200 - 0x21F, 16 x 32-bit edge sensitive counters, RO

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[[CategoryMlinkRegisters|MLinkRegisters]]