PCS/PMA CSR 1.0
Part of Network Port Registers
Registers |
|||
00h |
31:0 |
Identification |
RO |
02h |
31:0 |
Control |
R/W |
04h |
31:0 |
Status |
RO |
|
|||
10h |
31:0 |
Signal loss count |
RO |
12h |
31:0 |
Link down count |
RO |
14h |
31:0 |
High BER count |
RO |
|
|||
20h |
31:0 |
Uptime timer |
RO |
22h |
31:0 |
Signal change timer (status[0] toggle) |
RO |
24h |
31:0 |
Link flap timer (status[5] toggle) |
RO |
26h |
31:0 |
High BER timer (status[8] toggle) |
RO |
|
|||
30h |
7:0 |
pcs_err_block_count |
RO |
31h |
15:0 |
pcs_test_patt_err_count |
RO |
Timer resolution is 1 second
Register description
bit |
1G |
10G |
0 |
Signal detect (mirror of PHY CSR 1.0 status bit 1) |
|
1 |
PCS RX locked |
PCS RX locked LL (always 0) |
2 |
PCS RX locked |
|
3 |
PCS RX link status (always 0) |
|
4 |
10G PCS RX link status |
|
5 |
Auto-neg complete |
PMA link status |
8 |
disparity or BER |
PCS high BER |
9 |
|
PCS high BER LH |
10 |
|
PCS Bit Error |
11 |
|
PCS Pattern Error |
14:12 |
Speed |
|
15 |
Full-Duplex |
|
|
Speed decode
- 0 - 10M
- 1 - 100M
- 2 - 1G
- 4 - 10G