PHY CSR 1.0
Part of Network Port Registers
Registers |
|||
00h |
31:0 |
Identification |
RO |
02h |
31:0 |
Control |
R/W |
04h |
31:0 |
Status |
RO |
|
|||
10h |
31:0 |
Encoding error count |
RO |
|
|||
20h |
31:0 |
OSD flap timer (status[1] toggle) |
RO |
22h |
31:0 |
Link flap timer (status[11] toggle) |
RO |
Register description
Status register bits |
|
0 |
SFP inserted (inverted SFP_MOD_DETECT) |
1 |
SFP Signal Detect (inverted SFP_LOS) |
2 |
SFP_TX_FAULT |
3 |
SFP_TX_DISABLE |
7:4 |
speed (2: 1G) |
8 |
RX encoding error |
10:9 |
|
11 |
RX synchronized |
12 |
Loopback enabled |
13 |
GTX reset |
14 |
GTX reset complete |
15 |
GTX clock PLL locked |
19:16 |
|
24:20 |
bitslide value |
31:25 |
|