• MSC Input CSR

MSC Input CSR v1

• SDB Device ID 0xd26e4053

• Hardware MSC16VE

• MSC16VE Registers

• MSC Input CSR v2

Registers

• 00h - Control, R/W
  • [1] - counters lock
• 01h - Current state of external CE (TTL), RO
• 02h - Current state of input HITs, RO
• 0Dh - Number of input hit channels, RO static
• 0Eh - Number of histogramers, RO static
• 0Fh - Number of external CE inputs, RO static

In registers 0x80~0xBF times of last rising and falling edges of each external CE signal are stored. Time encoded in TAI 64-bit Timestamp.

• 80h - rising edge time of external CE #0, 64-bits, RO
• 84h - falling edge time of external CE #0, 64-bits, RO
• 88h - rising edge time of external CE #1, 64-bits, RO
• 8Ch - falling edge time of external CE #1, 64-bits, RO
• 90h - rising edge time of external CE #2, 64-bits, RO
• 94h - falling edge time of external CE #2, 64-bits, RO
• 98h - rising edge time of external CE #3, 64-bits, RO
• 9Ch - falling edge time of external CE #3, 64-bits, RO

Registers 0xC0~0xFF set crosspoint switching between any input channel to any internal histogram. Register address defines number of internal histogramer (lowest address is for histogram #0, next address - histogram #1, etc). Value of register defines input channel number.

• C0h - sets the number of input channel for histogram #0, R/W
• C1h - sets the number of input channel for histogram #1, R/W
• C2h - sets the number of input channel for histogram #2, R/W
• C3h - sets the number of input channel for histogram #3, R/W
• C4h - sets the number of input channel for histogram #4, R/W
• C5h - sets the number of input channel for histogram #5, R/W
• C6h - sets the number of input channel for histogram #6, R/W
• C7h - sets the number of input channel for histogram #7, R/W
• C8h - sets the number of input channel for histogram #8, R/W
• C9h - sets the number of input channel for histogram #9, R/W
• CAh - sets the number of input channel for histogram #10, R/W
• CBh - sets the number of input channel for histogram #11, R/W
• CCh - sets the number of input channel for histogram #12, R/W
• CDh - sets the number of input channel for histogram #13, R/W
• CEh - sets the number of input channel for histogram #14, R/W
• CFh - sets the number of input channel for histogram #15, R/W

Registers 0x100~17F are for Gate logic LUTs.

Each gate has it own LUT. Number of RegIO words for each LUT depends on the number of external count conditions (N_EXT_CE, Input CSR register 0xF): if N_EXT_CE is 4 of less, then number of RegIO words per LUT is 1, else use equation 2^(N_EXT_CE-4). There are no empty space between LUTs.

Assume that number of external count conditions is N, and in given time moment state of external count conditions is M. Steps to resolve LUT for each gate (LUT offset is known):

1. determine RegIO word number: (N>4) ? 2^(N-1)-1 : 0

2. determine exact output bit in word from previous step: M%16

Registers 0x180~1FF are for Count Enable LUTs. Same principle as for Gate LUTs

MSC SDB