Deserializers CSR
modules lib-serdes/rtl/adc_clk_csr
SDB Device ID 0x3efb27ee
Registers
- 00h, Control, 16 bits, R/W
- [15] ADC_RESET
- [14] DES_RESET
- [13] STATUS_RESET
- [12] ADC_SYNC (sync ADC after reconfiguration)
- [8] RESET (unused)
- 01h, Status, 16 bits, RO
- 03h, IDELAY_TAP_VAL, R/W
- 04h, IDELAY_LOAD_MASK, R/W
- clock wires: 0x5555
- data wires: 0xAAAA
- 05h, ADC_CH_INFO, RO, static
- [7:0] number of deserializers groups
- [15:8] channels per deserializer group