Board GPIO
SDB Device ID 0x35f39554
Register Map
address space 0x00 - 0xFF
00h - Identification 35f39554, 32 bits, RO
- 02h - reserved
03h, Lock, R/W
- [0] - update GPIO input (1: lock, 0: continuous update)
04h - Number of GPIO channels, RO
- 05h~3Fh - reserved
40h~4Fh - GPIO tristate capabilities, 256 bits, RO
bit # = channel #, actual number of channels has to be read from register 04h
50h~5Fh - GPIO input capabilities, 256 bits, RO
bit # = channel #, actual number of channels has to be read from register 04h
60h~6Fh - GPIO output capabilities, 256 bits, RO
bit # = channel #, actual number of channels has to be read from register 04h
- 70h~7Fh - reserved
80h~8Fh - GPIO tristate control, 256 bits, R/W
bit # = channel #, actual number of channels has to be read from register 04h
- '1' - set to input, '0' - set to output
90h~9Fh - GPIO input, 256 bits, RO
bit # = channel #, actual number of channels has to be read from register 04h
A0h~AFh - GPIO output, 256 bits, R/W
bit # = channel #, actual number of channels has to be read from register 04h
- B0h~FFh - reserved