TADC TDC Core Registers
RegIO
Base address - 0x0200, address mask - 0x00FF.
For detailed description see HPTDC Controller Registers
Reg 0x0000-0x001F - TDC Channels Enable, R/W
Reg 0x0020 - General Control (32-bit), R/W
- [0] - Standby and JTAG restart
- [31:1] - reserved
Reg 0x0022 - Read Control (32-bit), R/W
Reg 0x0024 - Measurement Control (32-bit), R/W
Reg 0x0026 - Trigger Windows Setup (32-bit), R/W
Reg 0x0028 - RC Adjust Setup (32-bit), R/W
Reg 0x002a - Test Pattern (32-bit), R/W
Reg 0x002с - General Status (32-bit), R/O
- [0] - HPTDC JTAG in standby
- [15:1] - reserved
- [24:16] - HPTDC error
- [31:25] - reserved
HPTDCs Status Registers
Reg 0x0080 - HPTDC #0, 1st Status Register
- [0] - Vernier Error
- [1] - Coarse Error
- [2] - Channel Select Error
- [3] - L1 Buffer Parity Error
- [4] - Trigger FIFO Parity Error
- [5] - Trigger Matching State Error
- [6] - Readout FIFO Parity Error
- [7] - Readout State Error
- [8] - Setup Parity Error
- [9] - Control Parity Error
- [10 - JTAG Instruction Error
- [11] - TDC Have Readout Token
- [12] - Readout FIFO Full
- [13] - Readout FIFO Empty
- [14] - Trigger FIFO Full
- [15] - Trigger FIFO Empty
Reg 0x0081 - HPTDC #0, 2nd Status Register
- [7:0] - Readout FIFO Occupancy
- [11:8] - Trigger FIFO Occupancy
- [12] - DLL Lock
- [13] - Inverted Setup bit 601
- [15:14] - reserved
Reg 0x0082 - HPTDC #0, 3rd Status Register
- [7:0] - Occupancy of L1 buffer of channel group 0
- [15:8] - Occupancy of L1 buffer of channel group 1
Reg 0x0083 - HPTDC #0, 4th Status Register
- [7:0] - Occupancy of L1 buffer of channel group 2
- [15:8] - Occupancy of L1 buffer of channel group 3
Reg 0x0084 - HPTDC #1, 1st Status Register
Reg 0x0085 - HPTDC #1, 2nd Status Register
Reg 0x0086 - HPTDC #1, 3rd Status Register
Reg 0x0087 - HPTDC #1, 4th Status Register
Reg 0x0088-0x00FF - same for every other HPTDC