Differences between revisions 7 and 8

Trigger Logic and Scaler Modules

model	standard	inputs	description
FVME2TMWR	VME64x	4 TTL 32 ECL/LVDS	41.667 MHz Clock source, trigger logic 4 majority units, 4 logic lanes, regular and random pulsers WhiteRabbit compatible
TTCM	VME64x	8 NIM 32 ECL/LVDS	40 MHz Clock source, trigger logic 4 majority units, 4 logic lanes, regular and random pulsers
MSC16V	VME64x	16 analog channels	Discriminator, multihit scaler with memory
MSC8E	Ethernet	8 analog channels	Discriminator, multihit scaler with memory

-  ⇤ ← Revision 7 as of 2014-05-07 12:32:07 → 
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  Editor: slepnev
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+   ← Revision 8 as of 2014-10-07 19:11:08 → ⇥
  Size: 1093
  Editor: slepnev
  Comment:
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-||<:>[[FVME2TM|{{attachment:fvme2tm-thm.png}}]]<<BR>>'''[[FVME2TM]]'''||VME64x||4 TTL<<BR>>32 ECL/LVDS||41.667 MHz Clock source, trigger logic<<BR>>4 majority units, 4 logic lanes, regular and random pulsers||
+||<:>[[FVME2TMWR|{{attachment:fvme2tm-thm.png}}]]<<BR>>'''[[FVME2TMWR]]'''||VME64x||4 TTL<<BR>>32 ECL/LVDS||41.667 MHz Clock source, trigger logic<<BR>>4 majority units, 4 logic lanes, regular and random pulsers<<BR>>[[WhiteRabbit]] compatible||