Waveform Recorder Module

• SDB Device ID 0x7477e01e

Register Map ver. 2.1

• 00h - Identification 7477e01e, 32 bits, RO static

• 02h - Control, R/W

  • [0] - softreset
  • [15:1] - reserved

• 03h, Lock, R/W

  • [0] - 1: lock, 0: continuous update

• 04h - Latency, R/W

• 05h - Match window, R/W

• 06h - reserved for ADC pre-window, R/W

• 07h - ADC window (samples to readout), R/W

• 08h - ADC mode, R/W

  • [0] disable zero suppression
  • [1] enable analog zero suppression
  • [2] enable digital zero suppression
  • [15:3] reserved

• 10h - Channel Enable, 128 bits, R/W

  • bit# = channel#

• 18h - Signal polarity, 128 bits, R/W

  • bit# = channel#

  • 0: active-high, 1: active-low

• 20h - Digital zero supression in channel enable, 128 bits, R/W

  • bit# = channel#

• 28h - Digital zero supression channel edge settings, 128 bits, R/W

  • bit# = channel#

  • 0: rising(save data > threshold), 1: falling(save data < threshold)

• 30h - ADC Build Params, 128 bits, RO static

  • [7:0] - reserved
  • [15:8] - ADC bits
  • [23:16] - ADC chips number
  • [31:24] - channel number per ADC chip
  • [39:32] - input ring buffer size in samples, log2 value, each channel (defines latency parameter)
  • [47:40] - event FIFO size in samples, log2 value, each channel (defines match window and ADC window parameters)
  • [63:48] - reserved
  • [95:64] - ADC discretization frequency, Hz
  • [127:96] - reserved

• 38h - Sparse control, added in v2.1, R/W

  • [0] - sparse enable
  • [15:1] - reserved

• 39h - Sparse read cell number, added in v2.1, R/W

  • redefine match window if sparse enabled

• 3Ah - Sparse period, added in v2.1, R/W

• 3Bh~3Fh - reserved

• 40h - ADC hfifo overflow, 128 bits, RO

  • bit# = channel#

• 48h - ADC mfifo overflow, 128 bits, RO

  • bit# = channel#

• 50h - ADC efifo overflow, 128 bits, RO

  • bit# = channel#

• 58h~7Fh - reserved

• 80~FFh - Digital zero suppression threshold, signed, R/W

  • one channel per address

  • channel #0 in addr 0x0080, channel #1 in addr 0x0081, etc.

Register Map ver. 1.0

Base address - 0x0300, address mask - 0x00FF.

• 01h - REG_ADC_MATCH_WIN

• 02h - REG_ADC_PREWIN

• 03h - REG_ADC_WIN - Samples to readout

• 04h - REG_ADC_MEM_DEPTH - in kilosamples (unused)

• 05h - REG_ADC_MODE , R/W

  • [1:0] - mode (1-norm,2-baseline)
  • [15:2] - reserved

• 06h - REG_ADC_GAIN_CRTL, R/W

  • [7:0] - for ch pairs
  • [15:8] - reserved

• 08h - REG64_ADC_CH_EN, R/W

• 10h - REG_ADC_BUILD_PARAM_1, RO

  • [7:0] - reserved
  • [15:8] - ADC bits

• 11h - REG_ADC_BUILD_PARAM_2, RO

  • [7:0] - ADC chips number
  • [15:8] - ADC chip channel number

• 12h - REG_ADC_BUILD_PARAM_3, RO

  • [7:0] - log2(max ADC latency)
  • [15:8] - log2(max ADC match window)

• 13h - REG_ADC_BUILD_PARAM_4 reserved, RO

• 40h - REG64_ADC_CH_HFIFO, RO

  • bit# = ch#

• 48h - REG64_ADC_CH_MFIFO, RO

  • bit# = ch#

• 50h - REG64_ADC_CH_EFIFO, RO

  • bit# = ch#

• 80h - REG_ADC_CH_DATA_BASE ADC Channel #0 Data, RO

SDB