Trigger Control

• SDB Device ID 0x76b80b88

Register Map

address space 0x00 - 0xFF0, default base address: 0x0100

• 00h - Identification 76b80b88, 32 bits, RO

• 02h - Control, 16 bits, R/W

  • [0] - softreset
  • [15:1] - reserved
• 03h - reserved

• 04h - Trigger Source Mask, 32 bits, R/W

• 06h - Trigger Source Capability, 32 bits, RO

• 08h - Trigger Polarity Mask, 32 bits, R/W

• 0Ah - Trigger Polarity Capability, 32 bits, RO

• 0Ch - Timer clock, Hz, 32 bits, RO

• 0Eh - Periodic pulser period, 32 bits, R/W

• 10h - Random pulser period, 32 bits, R/W

• 12h - Random pulser minimal period, 32 bits, R/W

• 14h - Programmed dead time, 32 bits, R/W

• 16h - Trigger Queue Length, 16 bits, RO

• 17h - Current Busy Status, 16 bits, RO

  • [0] - readout busy
  • [1] - tdc busy
  • [2] - adc busy
  • [3] - external veto
  • [4] - dead time
  • [15:5] - reserved

• 18h - Digital Threshold Trigger Delay, 16 bits, R/W

• 19h - Analog Threshold Trigger Delay, 16 bits, R/W

• 20h - Digital Threshold Channel Enable, 128 bits, R/W

• 28h - Digital Threshold Channel Polarity, 128 bits, R/W

• 30h - Analog Threshold Channel Enable, 128 bits, R/W

• 38h - Analog Threshold Channel Polarity, 128 bits, R/W

Trigger channels

• [0] - Digital threshold (Any Input Hit, masked)
• [1] - Analog threshold (comparator)
• [2] - VXS pulse (simple handshake)
• [3] - FE-Link over VXS
• [4] - Front-panel FE-Link
• [5] - External pulse (TTL)
• [6] - External pulse #2 (TTL)
• [7] - External pulse #3 (TTL)
• [8] - External pulse #4 (TTL)
• [9] - Digital logic trigger (added in v1.1)
• [13:10] - reserved
• [14] - Periodic pulser
• [15] - Random pulser

Polarity setting

• '0' - active-high polarity
• '1' - active-low polarity

SDB