TDC Core Registers TDC72 v1.0
SDB
- SDB Device ID 0x76b80b88
RegIO
Base address - 0x0200, address mask - 0x00FF.
For detailed description see HPTDC Controller Registers
Reg 0x0000 - TDC Channels ##64-71 Enable (32-bit), R/W
- [3:0] - channel #71 enable
- [7:4] - channel #70 enable
- [11:8] - channel #69 enable
- [15:12] - channel #68 enable
- [19:16] - channel #67 enable
- [23:20] - channel #66 enable
- [27:24] - channel #65 enable
- [31:28] - channel #64 enable
Reg 0x0002 - TDC Channels ##56-63 Enable (32-bit), R/W
Reg 0x0004 - TDC Channels ##48-55 Enable (32-bit), R/W
Reg 0x0006 - TDC Channels ##40-47 Enable (32-bit), R/W
Reg 0x0008 - TDC Channels ##32-39 Enable (32-bit), R/W
Reg 0x000a - TDC Channels ##24-31 Enable (32-bit), R/W
Reg 0x000c - TDC Channels ##16-23 Enable (32-bit), R/W
Reg 0x000e - TDC Channels ##8-15 Enable (32-bit), R/W
Reg 0x0010 - TDC Channels ##0-7 Enable (32-bit), R/W
Reg 0x0020 - General Control (32-bit), R/W
- [0] - Standby and JTAG restart
- [31:1] - reserved
Reg 0x0022 - Read Control (32-bit), R/W
Reg 0x0024 - Measurement Control (32-bit), R/W
Reg 0x0026 - Trigger Windows Setup (32-bit), R/W
Reg 0x0028 - RC Adjust Setup (32-bit), R/W
Reg 0x002a - Test Pattern (32-bit), R/W
Reg 0x002c - General Status (32-bit), R/O
- [0] - HPTDC JTAG in standby
- [15:1] - reserved
- [24:16] - HPTDC error
- [31:25] - reserved
HPTDCs Status Registers
Reg 0x0080 - HPTDC #0, 1st Status Register
- [0] - Vernier Error
- [1] - Coarse Error
- [2] - Channel Select Error
- [3] - L1 Buffer Parity Error
- [4] - Trigger FIFO Parity Error
- [5] - Trigger Matching State Error
- [6] - Readout FIFO Parity Error
- [7] - Readout State Error
- [8] - Setup Parity Error
- [9] - Control Parity Error
- [10] - JTAG Instruction Error
- [11] - TDC Have Readout Token
- [12] - Readout FIFO Full
- [13] - Readout FIFO Empty
- [14] - Trigger FIFO Full
- [15] - Trigger FIFO Empty
Reg 0x0081 - HPTDC #0, 2nd Status Register
- [7:0] - Readout FIFO Occupancy
- [11:8] - Trigger FIFO Occupancy
- [12] - DLL Lock
- [13] - Inverted Setup bit 601
- [15:14] - reserved
Reg 0x0082 - HPTDC #0, 3rd Status Register
- [7:0] - Occupancy of L1 buffer of channel group 0
- [15:8] - Occupancy of L1 buffer of channel group 1
Reg 0x0083 - HPTDC #0, 4th Status Register
- [7:0] - Occupancy of L1 buffer of channel group 2
- [15:8] - Occupancy of L1 buffer of channel group 3
Reg 0x0084~0x0087 - HPTDC #1, Status Registers
Reg 0x0088~0x008b - HPTDC #2, Status Registers
Reg 0x008c~0x008f - HPTDC #3, Status Registers
Reg 0x0090~0x0093 - HPTDC #4, Status Registers
Reg 0x0094~0x0094 - HPTDC #5, Status Registers
Reg 0x0098~0x009b - HPTDC #6, Status Registers
Reg 0x009c~0x009f - HPTDC #7, Status Registers
Reg 0x00a0~0x00a3 - HPTDC #8, Status Registers