TADC ADC Core Registers

Base address - 0x0300, address mask - 0x00FF.

Reg 0x0000 - Latency, R/W

Reg 0x0001 - Match window, R/W

Reg 0x0002 - reserved (for prewindow)

Reg 0x0003 - ADC Window (samples to readout), R/W

Reg 0x0004 - ADC channel memory depth, in kilosamples, RO

Reg 0x0005 - ADC mode, R/W

Reg 0x0006 - Input Gain Control, R/W

Reg 0x0007 - reserved

Reg 0x0008~0x000B - Channels enable (64-bits), R/W

Reg 0x0010 - ADC Build Param 1, RO

Reg 0x0011 - ADC Build Param 2, RO

Reg 0x0012 - ADC Build Param 3, RO

Reg 0x0013 - ADC Build Param 4, RO

Reg 0x0020 - ADC Pattern Test Control, R/W

Reg 0x0021 - ADC Test Pattern, msb alligned, R/W

Reg 0x0024~0x0027 - number of checked ADC words, 64-bits, RO

Reg 0x0028~0x002F - Mask of failed channels, 128-bits, RO

Reg 0x0040~0x0043 - ADC hfifo overflow (64-bits), bit# = ch#, RO

Reg 0x0048~0x004B - ADC mfifo overflow (64-bits), bit# = ch#, RO

Reg 0x0050~0x0053 - ADC efifo overflow (64-bits), bit# = ch#, RO

Reg 0x0080~0x00FF - ADC Channel Data, one register per channel, data is msb alligned, RO


MLinkRegisters

TADC ADC Core Registers (last edited 2021-09-23 16:01:28 by sav)