UT24VE MPD TRC

Registers are 16 bit width. 32-bit and 64-bit data is packed as following:

00h - Identification 8a3b62cd, 32 bits, RO static
04h - Number of input channels, RO static
05h - Number of physical triggers, RO static
08h - FHCAL East logic code, R/W
- [1:0] input logic: '0' - common OR, '1' - common AND, '2' - majority
- [15:8] threshold for majority logic
09h - FHCAL West logic code, R/W
- [1:0] input logic: '0' - common OR, '1' - common AND, '2' - majority
- [15:8] threshold for majority logic
0Ah - FHCAL Output logic code, R/W
- [0] FHCAL output logic: '0' - OR between East-West, '1' - AND between East-West
40h~7Fh - Input shapers values, R/W
- one register - one input channel
- actual number of registers read from register 04h (number of input channels)
80h~CFh - Input delays values, R/W
- one register - one input channel
- actual number of registers read from register 04h (number of input channels)
100h~1FFh - LUTs for physical triggers, R/W
- Number of words for LUT depends on number of physical triggers PHY_NCH (reg 05h: if PHY_NCH is 4 of less, then number of LUT words is 1, else use equation 2^(PHY_NCH-4)