FE-Link V2.0 CSR

FE-Link Wiki

FE-Link V1.0 CSR

• SDB Device ID 0x371a0421

Register map

• 00h, Identification 371a0421, 32 bits, RO static

• 02h, Control, R/W

  • [0] - reset

• 03h, Lock, R/W

  • [0] - 1: lock, 0: continuous update

• 04h, Number of channels, RO static

• 05h, Address of 1^st FE-Link channel registers, RO static

• 06h, Log2 address space per one FE-Link channel, RO static

One FE-Link channel registers

• 00h, Control, R/W

  • [0] - channel enable (enabled by default)
  • [1] - manual phase adjust enable (enabled by default)
  • [2] - automatic phase adjust enable (enabled by default, lower priority than automatic)
  • [13:2] - reserved
  • [14] - reset statistics (counters)
  • [15] - reset softpll

• 01h, PHY level control, R/W

  • [0] - manual reset PHY level
  • [1] - enable automatic PHY reset (enabled by default)
  • [15:2] - reserved

• 02h, Channel info, RO static

  • [7:0] - channel number
  • [11:8] - communication environment code (0: QSFP, 1: SFP, 2: VXS, other: reserved)
  • [14:12] - reserved
  • [15] - is master

• 03h, FE-Link protocol version, RO static

  • [3:0] - minor version
  • [7:4] - major version
  • [15:8] - reserved

• 04h, Status, RO

  • [0] - PHY level sync
  • [1] - rx sync (remote device PHY level sync)
  • [2] - remote rx sync (remote device verified our PHY level sync)
  • [3] - softpll locked (only for time receiving side)
  • [4] - link ok
  • [7:5] - reserved
  • [8] - SFP inserted (inverted SFP_MOD_DETECT)
  • [9] - SFP Signal Detect (inverted SFP_LOS)
  • [10] - SFP_TX_FAULT
  • [11] - SFP_TX_DISABLE
  • [12:5] - reserved
• 05h, reserved

• 06h, RX Bitslide, RO

• 07h, Remote Protocol Version, RO

  • [3:0] - minor version
  • [7:4] - major version
  • [15:8] - reserved

• 08h, Remote ID, 64 bits, RO

  • [47:0] - Serial ID

  • [55:48] - Device ID

  • [63:56] - reserved
• 0Ch~0Fh, reserved

• 10h, Current link state time, milliseconds, 32 bits, RO

• 12h, SYNC resend time, microseconds, 10000 µs by default, R/W

• 13h, Timeout for time frame receiving, milliseconds, 3000 ms by default, R/W

• 14h, Counter up step for received bad packets, default 10, R/W

• 15h, Bad packets couter threshold, default 99, R/W

• 16h, SYNC receive timeout, milliseconds, default 2000, R/W

• 17h~1Fh, reserved

• 20h, GTX Control, 32 bits, R/W

  • [0] - GTX reset
  • [3:1] - LOOPBACK
  • [5:4] - RXPD
  • [7:6] - TXPD

• 22h, GTX Status, 32 bits, RO

  • [2:0] - encoded CPLL reset state
  • [3] - CPLLLOCK
  • [4] - CPLLREFCLKLOST
  • [5] - CPLLPD
  • [6] - CPLLRESET
  • [7] - CPLL ready
  • [10:8] - encoded TX reset state
  • [11] - TX ready
  • [12] - TX reset done
  • [13] - GTTXRESET
  • [16:14] - encoded RX reset state
  • [17] - RX ready
  • [18] - RX reset done
  • [19] - GTRXRESET
  • [20] - RX CDR lock
  • [21] - RX comma detect
  • [22] - RX byte alligned
  • [23] - RX synced
  • [24] - GTX ready
  • [31:25] - reserved
• 23h~3Fh, reserved

Registers 40h~7Fh are for 32 bits counter

• 40h, RX code error counter, 32 bits, RO

• 42h, RX CRC error counter, 32 bits, RO

• 44h, SYNC frame sent counter, 32 bits, RO

• 46h, SYNC frame received counter, 32 bits, RO

• 48h, TIME frame sent counter, 32 bits, RO

• 4Ah, TIME frame received counter, 32 bits, RO

• 4Ch, TRIG frame sent counter, 32 bits, RO

• 4Eh, TRIG frame received counter, 32 bits, RO

• 50h, Unknown frame received counter, 32 bits, RO

• 52h, Reset PHY counter, 32 bits, RO

• 54h~7F, reserved

SDB