CCPC (4,5,7) Programming Reference
CCPC interface is implemented within x86 ISA I/O space. There are 4 16-bit registers with base address 0x360. By reading and writing data to/from these registers one can generate CAMAC cycles and read controller status.
Register description
I/O port 0x360 - data (bits 0-15) |
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bit |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
Read |
R16 |
R15 |
R14 |
R13 |
R12 |
R11 |
R10 |
R9 |
R8 |
R7 |
R6 |
R5 |
R4 |
R3 |
R2 |
R1 |
Write |
W16 |
W15 |
W14 |
W13 |
W12 |
W11 |
W10 |
W9 |
W8 |
W7 |
W6 |
W5 |
W4 |
W3 |
W2 |
W1 |
I/O port 0x362 - data (bits 16-23) and status |
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bit |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
Read |
INF |
ExtLAM |
L22 |
L21 |
L20 |
L19 |
L18 |
L17 |
R24 |
R23 |
R22 |
R21 |
R20 |
R19 |
R18 |
R17 |
Write |
W24 |
W23 |
W22 |
W21 |
W20 |
W19 |
W18 |
W17 |
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I/O port 0x364 - control and status, CCPC4/CCPC5 |
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bit |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
Read |
L |
X |
Q |
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Write |
OUTF |
Inhibit |
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I/O port 0x364 - control and status, CCPC7 |
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bit |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
Read |
INF1 |
INF2 |
|
CCPC version |
R24 |
R23 |
R22 |
R21 |
R20 |
R19 |
R18 |
R17 |
L23 |
L |
X |
Q |
Write |
INF1 as EXTL |
INF2 as EXTL |
IRQ11 enable |
OUTF2 |
OUTF1 |
Inhibit |
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I/O port 0x366 - NAF, bus cycle |
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bit |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
Read |
L16 |
L15 |
L14 |
L13 |
L12 |
L11 |
L10 |
L9 |
L8 |
L7 |
L6 |
L5 |
L4 |
L3 |
L2 |
L1 |
Write |
C |
Z |
N16 |
N8 |
N4 |
N2 |
N1 |
A8 |
A4 |
A2 |
A1 |
F16 |
F8 |
F4 |
F2 |
F1 |
I/O port 0x368 - control flags, CCPC7 |
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bit |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
Read |
INF1 as EXTL |
INF2 as EXTL |
IRQ11 enable |
OUTF2 |
OUTF1 |
Inhibit |
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CAMAC bus cycle is generated only while writing NAF register (port 0x366). Accessing other registers does not generate CAMAC bus cycles.