= Waveform Baseline Correction =

 * [[SDB Device ID]] 0xc32e925e

==== Register Map ====

address space 0x000 - 0x1FF

 * 00h - '''Identification''' ''c32e925e'', 32 bits, RO static

 * 02h - '''Control''', R/W
   . [0] - reset

 * 03h - '''Lock''', R/W

   . [0] - 1: lock, 0: continuous update

 * 04h - '''Number of channels''', RO static
 * 05h - '''Common baseline offset''', 16 bits signed, R/W (since ver 1.1)
 * 08h - '''Input raw data''' array address, RO static
 * 09h - '''Static Offset Compensation''' array address, RO static
 * 0Ah - '''BLC Settings''' array address, RO static
 * 0Bh - '''BLC Low Threshold''' array address, RO static
 * 0Ch - '''BLC Hight Threshold''' array address, RO static

==== Arrays of Channel Registers ====

 * '''Input raw data''', 16 bits signed, RO

 * '''Static Offset Compensation''', 16 bits signed, R/W

 * '''BLC Settings''', R/W
   . [4..0] - MAF width (0: 1 sample, 0x1F: 32 samples)
   . [10:8] - MAF roundoff, number of bits to truncate, 0..7
   . [13:12] - output select (0: bypass, 1: BLC output, 2: debug, 3: MAF output)
   . [14] - Signal Polarity (0: positive, 1: negative)
   . [15] - BLC enable (0: bypass, 1: enable)

 * '''BLC Low Threshold''', 16 bits signed, R/W

 * '''BLC High Threshold''', 16 bits signed, R/W

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[[CategorySDB|SDB]]