= TQDC-16 VME module registers, firmware v2.0 =

Previous version: [[VmeRegistersTqdc16v1|Firmware v1.0]]

Hardware: [[TQDC-16]]

||<tablewidth="60%" : -4>AM 0x29 (A16 D32) Registers||
||Reg||Address||Name||Access||
||0||0x0000||Control||R/W||
||1||0x0004||ADCSet0||R/W||
||2||0x0008||ADCSet1||R/W||
||3||0x000C||JTAG||R/W||
||4||0x0010||[[#TRIGSet|TRIGSet]]||R/W||
||5||0x0014||DACSet||R/W||
||6||0x0018||ADCLat||R/W||
||7||0x001C||factory test||R/W||
||8||0x0020||JTAG32||R/W||
||9||0x0024||Status||Read Only||
||10||0x0028||Compstate||Read Only||
||11||0x002C||ADC Window||R/W||
||12||0x0030||TQDC16VS gain control||R/W||
||<:-4>unused||
||16||0x0040||Serial_ID_lo||Read Only||
||17||0x0044||Serial_ID_hi||Read Only||
||18||0x0048||Temperature_1||Read Only||
||<:-4>unused||
||32||0x0080||ADC 0 data||Read Only||
||<:-4>...||
||47||0x00BC||ADC 15 data||Read Only||

||<tablewidth="50%" : -3>AM 0x39 (A24 D32) Registers||
||Reg||Address||Name||
||0||0x000000||Trigger Logic RAM 0, word 0||
||<:-3>...||
||7||0x00001C||Trigger Logic RAM 0, word 7||
||8||0x000020||Trigger Logic RAM 1, word 0||
||<:-3>...||
||15||0x00003C||Trigger Logic RAM 1, word 7||
||200||0x000800||Counter0||
||<:-3>...||
||215||0x00083C||Counter15||


Supports [[VmeInterfaceGeneral|base registers]]: Control, JTAG, JTAG32, Status, Serial_ID_1, Temperature_1.

Status register supports bits: 0, 2, 3.

== Additional Registers ==
AM 0x29, A16 D32

Reg 1, @0x0004, ADCSet0, R/W

ADC device 0, channels 0..7
 . [9:0] search window
 . [14:10] --(match window)--
 . [15] input polarity (1=negative)
 . [23:16] channels 7:0 enable mask
 . [29:28] --(device number ('device' field in raw data), set to 1)-- set to 0
 . [31:30] mode

Reg 2, @0x0008, ADCSet1, R/W

ADC device 1, channels 8..15
 . [9:0] --(search window)--
 . [14:10] --(match window)--
 . [15] input polarity (1=negative)
 . [23:16] channels 15:8 enable mask
 . [29:28] --(device number ('device' field in raw data), set to 2)-- set to 0
 . [31:30] mode

<<Anchor(TRIGSet)>>
Reg 4, @0x0010, TRIGSet, R/W
 . [3:0] hit matching width
 . [7:4] select channel A for ST trigger
 . [11:8] select channel B for ST trigger
 . [12] ST channel A enable
 . [13] ST channel B enable
 . [14] reserved
 . [15] 1 - AND matching, 0 - XOR matching (?)
 . [31:16] channels 15:0 enable mask for trigger logic

Reg 5, @0x0014, DACSet, R/W
 . [15:0] DAC data
 . [16] select: 0 - channels 7:0, 1 - channels 15:8
 . [17] LDAC (load command)

Reg 6, @0x0018, ADCLat, R/W
 . [31:0] ADC trigger latency, complementary code

Reg 10, @0x0028, Compstate, Read only
 . [15:0] input discriminator state

Reg 11, @0x002C, ADC Window, R/W
 . [31:0] ADC Window (approx 1.5us max)

Reg 32..Reg 47, @0x0080..@0x00BC, ADC instant data
 . [5:0] reserved 0
 . [15:6] ADC raw sample data
 . [31:16] reserved

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[[CategoryVmedaqRegisters|VMEDAQ Registers]]