= MTDC-64 Module Registers =

||<tablewidth="60%" : -4>AM 0x29 (A16 D32) Registers||
||Reg||Address||Name||Access||
||0||0x0000||Control||R/W||
||1||0x0004||Test||R/W||
||<:-4>..||
||3||0x000C||JTAG||R/W||
||<:-4>..||
||8||0x0020||JTAG32||R/W||
||9||0x0024||Status||Read Only||
||10||0x0028||Channel 0-31 enable mask||R/W||
||11||0x002C||Channel 32-63 enable mask||R/W||

Registers 0..9 are compatible with [[VmeRegistersTdc|TDC Registers]].

Supports [[VmeInterfaceGeneral|base registers]]: Control, JTAG, JTAG32, Status.

Status register supports bits: 0 (TTC clock status), 1 (device Ok), 2 (subdevice #0 Ok), 3..7 - optional.

== Additional Registers ==
AM 0x29, A16 D32

Write 0 to all reserved values.

Reg 1, @0x0004, TEST, R/W

 . [31:0] read/write dummy test register

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[[CategoryVmedaqRegisters|VMEDAQ Registers]]