<> = U40VE-RC module registers v2.0 = Hardware: [[U40VE-RC]] [[UT24VE-RC]] == Memory I/O == ||'''word address'''||'''Description'''|| ||0x000000-0x001FFF||Spill Plot RAM|| ||0x010000-0x0103FF||Time b/w trigger Plot RAM|| Registers are 16 bit width. 32-bit and 64-bit data is packed as following: ||Reg #||64-bit word|| ||0x70||bits 15:0|| ||0x71||bits 31:16|| ||0x72||bits 47:32|| ||0x73||bits 63:48|| == Register I/O == ||'''address'''||'''Description'''|| ||0x40-0x5F||[[MlinkCsr|M-Link CSR]]|| ||0x60-0x7F||[[WR_Status_Registers|WR Status]]|| ||0x80-0xBF||[[#SYS_REG_RC|Run Control Registers]]|| ||0xC0-0xFF||[[Spill Control Module]]|| ||0x800-0x83F||Time Counters (Total)|| ||0x840-0x87F||Edge Counters (Total)|| ||0x880-0x8BF||Time Counters (Run)|| ||0x8C0-0x8FF||Edge Counters (Run)|| ||0x900-0x93F||Time Counters (Spill)|| ||0x940-0x97F||Edge Counters (Spill)|| ||0x980-0x9BF||Time Counters (Run & Spill)|| ||0x9C0-0x9FF||Edge Counters (Run & Spill)|| ||0xA00-0xA3F||Edge Counters (XOFF high timeout)|| ||0xB00-0xB3F||Edge Counters (XOFF low timeout)|| ||0xC00-0xC3F||Edge Counters (15 unused + Hamming code errors)|| ||0xD00-0xD3F||Edge Counters (15 unused + event number)|| == 0x40 - 0x5F — M-Link CSR == Reg 0x40, CTRL, R/W . [0] - softclear (clear statistics) . [1] - counters lock (0 - counters enable, 1 - lock) . [2] - enable Hamming code error count . [15:3] - reserved Reg 0x42, DEVICE_ID, RO . [15:8] - [[DeviceId|device id]] . [7:0] - reserved (0) Reg 0x43, Live Magic, R/W . [15:0] - data Reg 0x50, SERIAL_ID, 64-bit Board Serial Number (DS18B20), RO Reg 0x54, TEMPERATURE, current temperature, RO Reg 0x55, reserved, RO Reg 0x56, FW_VER, 16-bit, firmware version number, RO Reg 0x57, FW_REV, 16-bit, firmware revision number, RO == 0x60 - 0x7F — WR Status == [[WR_Status_Registers|WR Status]] <> == 0x80 - 0xBF — Run Control == Reg 0x80, rc_ctrl, R/W . [0] - clear . [13:1] - reserved (0) . [14] - soft spill enable (default disable 0) . [15] - run enable (default 1) Reg 0x81, channel count, RO Reg 0x82, trigger source select, R/W . [0] - LEMO input . [13:1] - reserved . [14] - random pulser . [15] - fixed frequency pulser Reg 0x83, trigger state, RO Reg 0x84, xoff input mask, R/W Reg 0x85, xoff input state, RO Reg 0x86, trigger output mask, R/W Reg 0x87, xoff timeout state, RO Reg 0x88-0x89, fixed frequency pulser period, R/W Reg 0x8A-0x8B, random pulser probability, R/W Reg 0x8C-0x8F reserved Reg 0x90-0x91, spill plot current ram address, RO Reg 0x92-0x93, spill plot step value (clocks), R/W Reg 0x94-0x95, triger time histogram step (clocks), R/W Reg 0x96, Plot source, R/W . [4:0] Spill and triger time plot source . 0-13 - Input pulse count frm selected channel . 14 - Trigger candidate count . 15 - Accepted trigger count . [15:4] - reserved Reg 0x96, LVDS trigger mask, R/W Reg 0x97 - reserved Reg 0x9A-0x9B - PDead, R/W Reg 0x9C-0x9D - tih s1, R/W Reg 0x9E-0x9F - tih s2, R/W reg 0xA0-0xA7 - Build Pararameter Structure, RO reg 0xA8-0xAB - Event Number Load (64-bit), R/W . ''Event number will be updated when writing into reg 0x0017 performed'' Reg 0xAC-0xAF - Current Event Number (64-bit), RO Reg 0xB0-0xBF reserved <> == Counters == Time Counters: 16 x 64-bit level sensitive counters, RO ||Counter||Description|| ||0||Channel 0 XOFF time|| ||…||…|| ||13||Channel 13 XOFF time|| ||14||Resulting XOFF time|| ||15||Elapsed time|| Edge Counters: 16 x 64-bit edge sensitive counters, RO ||Counter||Description|| ||0||Input 0 pulse count|| ||…||…|| ||13||Input 13 pulse count|| ||14||Trigger candidate count|| ||15||Accepted trigger count|| ---- [[CategoryMlinkRegisters|MLinkRegisters]]