#<> = TQDC16VS-E module registers v2 = * Hardware: [[TQDC16VS-E]] * SDB * [[https://afi-git.jinr.ru/fpga/tqdc/-/blob/devel/top/tqdc16vs_v2_wr/tqdc16vs_v2_wr.sdb.csv]] (Git) * [[attachment:tqdc16vs_v2_wr.sdb.csv]] (copy) '''In progress: migration to [[TADC_System_Registers|TADC System Register]]''' Registers are 16 bit width. 32-bit and 64-bit data is packed as following: ||Reg # ||64-bit word || ||0x70 ||bits 15:0 || ||0x71 ||bits 31:16 || ||0x72 ||bits 47:32 || ||0x73 ||bits 63:48 || ---- [[CategoryMlinkRegisters|MLinkRegisters]]