#<> = TQDC16VS-E module registers v1 = Hardware: [[TQDC16VS-E]] Registers are 16 bit width. 32-bit and 64-bit data is packed as following: ||Reg # ||64-bit word || ||0x70 ||bits 15:0 || ||0x71 ||bits 31:16 || ||0x72 ||bits 47:32 || ||0x73 ||bits 63:48 || == Register I/O == ||<-32 rowclass="bits">[[#SYS_REGS|System Registers]], 0x0000 - 0x3FFF|| ||<:>Address range||<:>Module || ||0x0040 - 0x005F ||[[TQDC16VS-E CSR]] || ||0x0060 - 0x007F ||[[#RUN_LOGIC|Run Logic]] || ||0x0100 - 0x01FF ||[[#SYS_REG_TRG|Trigger control & statistic]]|| ||0x0200 - 0x02FF ||[[TDC Core Registers TQDC16VS v1.0]] || ||0x0300 - 0x03FF ||[[#SYS_REG_ADC|ADC Core Registers]] || ||0x0400 - 0x04FF ||[[#SYS_REG_WRE|WR Time Emulator Registers]] || ||0x0500 - 0x05FF ||[[#SYS_REG_DES|Deserializers]] || ||0x0600 - 0x06FF ||[[#SYS_REG_HIT|Input Hit Coutners]] || ||0x0700 - 0x07FF ||reserved|| ||0x0800 - 0x08FF ||[[WR_Status_Registers|White Rabbit Status Registers]]|| ||0x0900 - 0x09FF ||reserved|| ||0x1000 - 0x10FF ||[[HWIP_Error_Counters|HWIP Error Counters]] (added in 2.1.43)|| ||<-32 rowclass="bits">[[#BOARD_REGS|Board Level Registers]], 0x4000 - 0x7FFF|| ||<:>Address range ||<:>Module || ||0x4000 - 0x40FF ||[[MCU Registers v1.0]] || ||0x4100 - 0x41FF ||[[#ADC_SPI|SPI communication to ADCs]] || ||0x4200 - 0x42FF ||[[#DAC_THR|Thresholds setup]] || ||0x4300 - 0x43FF ||Clock CSR (TQDC16VS_V2 only) || ||0x4400 - 0x44FF ||[[#TTL_SEL|TTL I/O Setup]] || ||0x7000 - 0x70FF ||[[SPI_NOR_Flash_Programmer|Flash Programmer]]|| ---- ---- <> == System Registers == '''Base address - 0x0000, address mask - 0x3FFF.''' ---- <> === Run Logic === '''Base address - 0x0060, address mask - 0x001F.''' Reg 0, @0x0000 - Run Mode, R/W . all bits are '0' - normal mode, run stops from software . [0] - time limit mode . [1] - event number limit mode Reg 1, @0x0001 - Run State, RO . [0] - '1' run is active, '0' not in run Reg 2, @0x0002 - reserved Reg 3, @0x0003 - reserved Reg 4, @0x0004 - run start time code in TAI (64 bits), RO . [63:32] - seconds since Epoch . [31:2] - nanoseconds . [1:0] - flags: 2 - time valid, others - time invalid Reg 5, @0x0008 - run time limit in milliseconds (32 bits), R/W Reg 6, @0x000A - run event number limit (32 bits), R/W ---- <> === Trigger control & statistic === '''Base address - 0x0100, address mask - 0x00FF.''' Reg 0x0000 - Trigger CSR, R/W . [0] - trigger counters reset . [1] - run trigger counters reset . [2] - trigger counters lock . [3] - run time reset . [15:4] - reserved Reg 0x0001 - Trigger Source, R/W . [0] - Timer . [1] - LEMO . [2] - TTC . [3] - Self Trigger (Any Input Hit, masked) . [4] - VXS (add in version 2.1.43) . [5] - FELink (add in version 2.1.43) . [15:6] - reserved Reg 0x0002 - Trigger Timer Period (32-bit), 8 ns step, R/W Reg 0x0004 - Event Number Load (32-bit), R/W Reg 0x0006 - Queue of Triggers to Readout, RO . [4:0] - Triggers queue . [15:5] - reserved Reg 0x0007 - Self Trigger Hit Mask, R/W Reg 0x0008 - Self Trigger Delay (8 ns step, 1us max), R/W Reg 0x0009 - Current Busy Status, RO . [0] - readout busy . [1] - tdc busy . [2] - adc busy . [3] - external busy (LEMO input) . [15:4] - reserved Reg 0x000a~0x000f - reserved Reg 0x0010 - All Trigger Candidates Counter (64-bit), RO Reg 0x0014 - Run Trigger Candidates Counter (64-bit), RO Reg 0x0018 - Accepted Trigger Counter (64-bit), RO Reg 0x001C - Run Time in nanoseconds (64-bit), RO ---- <> === ADC Core Registers === '''Base address - 0x0300, address mask - 0x00FF.''' Reg 0x0000 - Latency, R/W Reg 0x0001 - Match window, R/W Reg 0x0002 - reserved Reg 0x0003 - ADC Window (samples to readout), R/W Reg 0x0004 - Channels enable, R/W Reg 0x0005 - ADC mode, R/W . [1:0] - '0' reserved, '1' normal, '2' baseline, '3' reserved . [15:2] - reserved Reg 0x0006 - Input Gain Control, R/W . [0] - channels 1-2 gain: 0 - x1 gain, 1 - x4 gain . [1] - channels 3-4 gain: 0 - x1 gain, 1 - x4 gain . [2] - channels 5-6 gain: 0 - x1 gain, 1 - x4 gain . [3] - channels 7-8 gain: 0 - x1 gain, 1 - x4 gain . [4] - channels 9-10 gain: 0 - x1 gain, 1 - x4 gain . [5] - channels 11-12 gain: 0 - x1 gain, 1 - x4 gain . [6] - channels 13-14 gain: 0 - x1 gain, 1 - x4 gain . [7] - channels 15-16 gain: 0 - x1 gain, 1 - x4 gain . [15:8] - reserved Reg 0x0007 - Input Signal Polarity, R/W . 1 - negative, 0 - positive Reg 0x0020 - ADC Pattern Test Control, R/W . [0] - test enable (resets previous results, when started new test) . [1] - pause test . [15:2] - reserved Reg 0x0021 - ADC Test Pattern, msb alligned, R/W Reg 0x0024~0x0027 - number of checked ADC words, 64-bits, RO Reg 0x0028~0x002F - Mask of failed channels, 128-bits, RO . ''Bit number == channel number, set if ADC word not equal to test pattern'' Reg 0x003E - Comparators State, RO Reg 0x0040 - ADC hfifo overflow, bit# = ch#, RO Reg 0x0041 - ADC mfifo overflow, bit# = ch#, RO Reg 0x0042 - ADC efifo overflow, bit# = ch#, RO Reg 0x00F0 - ADC Channel #0 Data, RO Reg 0x00F1 - ADC Channel #1 Data, RO Reg 0x00F2 - ADC Channel #2 Data, RO Reg 0x00F3 - ADC Channel #3 Data, RO Reg 0x00F4 - ADC Channel #4 Data, RO Reg 0x00F5 - ADC Channel #5 Data, RO Reg 0x00F6 - ADC Channel #6 Data, RO Reg 0x00F7 - ADC Channel #7 Data, RO Reg 0x00F8 - ADC Channel #8 Data, RO Reg 0x00F9 - ADC Channel #9 Data, RO Reg 0x00FA - ADC Channel #10 Data, RO Reg 0x00FB - ADC Channel #11 Data, RO Reg 0x00FC - ADC Channel #12 Data, RO Reg 0x00FD - ADC Channel #13 Data, RO Reg 0x00FE - ADC Channel #14 Data, RO Reg 0x00FF - ADC Channel #15 Data, RO ---- <> === WR Time Emulator Registers === '''Base address - 0x0400, address mask - 0x00FF.''' Reg 0x0000 - TAI Seconds [15:0], R/W Reg 0x0001 - TAI Seconds [31:16], R/W Reg 0x0002 - TAI Seconds [39:32], R/W ---- <> === Deserializers control === '''Base address - 0x0500, address mask - 0x00FF.''' Reg 0x0000 - Deserializer control, R/W . [15] - INC . [14] - ADC Reset . [13] - Status Reset . [12] - Reset Reg 0x0001 - Deserializer status, R . [7:0] - ADC lock status . [15:8] - ADC ramp error Reg 0x03 - IDELAY_TAP_VAL Reg 0x04 - IDELAY_LOAD_MASK ---- <> === Input Hit Counters === '''Base address - 0x0600, address mask - 0x00FF.''' Reg 0x0000 - Hit Counters Control, R/W . [0] - Counters lock . [15:1] - reserved Reg 0x0004 - Counters Timestamp, 8ns period (64-bits), RO . [47:0] - timestamp . [63:48] - reserved Reg 0x0080 - Channel #1 Hit Counter (32-bits), RO Reg 0x0082 - Channel #2 Hit Counter (32-bits), RO Reg 0x0084 - Channel #3 Hit Counter (32-bits), RO Reg 0x0086 - Channel #4 Hit Counter (32-bits), RO Reg 0x0088 - Channel #5 Hit Counter (32-bits), RO Reg 0x008A - Channel #6 Hit Counter (32-bits), RO Reg 0x008C - Channel #7 Hit Counter (32-bits), RO Reg 0x008E - Channel #8 Hit Counter (32-bits), RO Reg 0x0090 - Channel #9 Hit Counter (32-bits), RO Reg 0x0092 - Channel #10 Hit Counter (32-bits), RO Reg 0x0094 - Channel #11 Hit Counter (32-bits), RO Reg 0x0096 - Channel #12 Hit Counter (32-bits), RO Reg 0x0098 - Channel #13 Hit Counter (32-bits), RO Reg 0x009A - Channel #14 Hit Counter (32-bits), RO Reg 0x009C - Channel #15 Hit Counter (32-bits), RO Reg 0x009E - Channel #16 Hit Counter (32-bits), RO ---- <> === White Rabbit Status Registers === ''Added in version 2.1.43'' * '''Base address - 0x0800, address mask - 0x00FF.''' * [[WR_Status_Registers|WR Status Registers]] * Module specific register 0x000E: Number of Divider-by-3 Synchronization Error events <> ---- ---- <> == Board Level Registers == '''Base address - 0x4000, address mask - 0x3FFF.''' ---- <> === SPI communication to ADCs === '''Base address - 0x0100, address mask - 0x000F.''' Reg 0, @0x0000, ADC0 SPI address, R/W . [6:0] SPI address . [7] SPI read/write command (1 - read) . [15:8] reserved Reg 1, @0x0001, ADC0 SPI write data, R/W . [7:0] SPI write data . [15:8] reserved Reg 2, @0x0002, ADC0 SPI read data, R/W . [7:0] data from registers related to ADC channels 1 4 5 8 . [15:8] data from registers related to ADC channels 2 3 6 7 Reg 8, @0x0008, ADC1 address, R/W . [6:0] SPI address . [7] SPI read/write command (1 - read) . [15:8] reserved Reg 9, @0x0009, ADC1 write data, R/W . [7:0] SPI write data . [15:8] reserved Reg 10, @0x000A, ADC1 SPI read data, R/W . [7:0] data from registers related to ADC channels 1 4 5 8 . [15:8] data from registers related to ADC channels 2 3 6 7 ---- <> === Thresholds setup === '''Base address - 0x0200, address mask - 0x000F.''' Reg 0, @0x0000, Thresholds setup for channels 0..7, R/W [15:0] DAC data Reg 1, @0x0001, Thresholds setup for channels 8..15, R/W [15:0] DAC data ---- <> === TTL I/O Setup === '''Base address - 0x0400, address mask - 0x00FF.''' Reg 0, @0x0000, TTL I/O channels number, RO Other registers: Reg # - TTL I/O #, R/W . [14:0] - input or output selector . [15] - output enable: 1 - output, 0 - input Selector decode for inputs . 0 - trigger input . 1 - busy input . 2 - active-low busy input . 3 - event number reset input Selector decode for outputs . 0 - accepted trigger . 1 - blocked trigger . 2 - busy . 3 - pps (only for WR compatible boards) . 4 - pulse, period 24 ns (p24ns) (only for WR compatible boards) . 5 - pulse, period 48 ns (p48ns) (only for WR compatible boards) . 6 - Logic 0 . 7 - Logic 1 ------ [[CategoryMlinkRegisters|MLinkRegisters]]