= TLU40LVDS registers =

Hardware: [[TLU40LVDS]]

Registers are 16 bit width. 32-bit and 64-bit data is packed as following:
||Reg # ||64-bit word ||
||0x70  ||bits 15:0   ||
||0x71  ||bits 31:16  ||
||0x72  ||bits 47:32  ||
||0x73  ||bits 63:48  ||

== Register I/O ==

||<:>Address range||<:>Module                            ||
||0x0040 - 0x005F ||[[MlinkCsr|M-Link CSR]]              ||
||0x0200 - 0x03FF ||[[TLU40LVDS TOF Trigger CSR]]        ||
||0x0400 - 0x05FF ||[[TLU40LVDS Luminosity Trigger CSR]] ||
||0x4000 - 0x40FF ||[[MCU Registers v2.0]]               ||
||0x4100 - 0x41FF ||[[TLU TTL I/O Control]]              ||
||0x5000 - 0x50FF ||[[WR Time Emulator]]                 ||
||0x5100 - 0x51FF ||[[WR_Status_Registers|WR Status]]    ||
||0x6000 - 0x61FF ||[[FE-Link V2.0 CSR]]                 ||
||0x7000 - 0x70FF ||[[SPI_NOR_Flash_Programmer|Flash Programmer]]||
||0x7200 - 0x73FF ||[[Network Port Registers]]           ||
||0x7600 - 0x77FF ||[[Network Port Registers|Network Port Registers (Fe-Link)]] ||
||0x7C00 - 0x7CFF ||[[CategorySDB|FPGA Configuration Space (SDB)]] ||

----
[[CategorySDB|SDB]] [[CategoryTLU|TLU]]