TDC72VXS Data Format

Hardware TDC72VXS

TDC72VXS payload data is encapsulated in M-Stream 2.2 protocol using Data Subtype 0.

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Event Data format

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Data Block format

• TDC Data Block

• Statistic Data Block

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TDC Data Block

• Data Type is 0x0

TDC Data Block specific bits:

• [27:17] - reserved
• [16] - event FIFO overflow

TDC Data Payload

TDC event header and TDC event trailer are optional and in most cases will not be used.

TDC timestamp in number of 25 ns time intervals since global trigger timestamp found in event header.

• E = 0 - leading egde.
• E = 1 - trailing egde.

TDC time measurement

• data bits [20:2] = number of 100 ps time intervals since global trigger timestamp found in event header;
• data bits [1:0] = rcdata[1:0].

TDC error flags bits:

• [0] Hit lost in group 0 from read-out fifo overflow
• [1] Hit lost in group 0 from L1 buffer overflow
• [2] Hit error have been detected in group 0
• [3] Hit lost in group 1 from read-out fifo overflow
• [4] Hit lost in group 1 from L1 buffer overflow
• [5] Hit error have been detected in group 1
• [6] Hit lost in group 2 from read-out fifo overflow
• [7] Hit lost in group 2 from L1 buffer overflow
• [8] Hit error have been detected in group 2
• [9] Hit lost in group 3 from read-out fifo overflow
• [10] Hit lost in group 3 from L1 buffer overflow
• [11] Hit error have been detected in group 3
• [12] Hits rejected because of programmed event size limit
• [13] Event lost (trigger FIFO ovefrlow)
• [14] Internal fatal chip error has been detected

Most important error bits are 12 and 13. Error bit 14 should be ignored.

For detailed description of TDC please refer to HPTDC manual.

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Statistic Data Block

• Data Type is 0xF

Statistic Data Block specific bits:

• [27:18] - reserved
• [17] - RegIO Error
• [16] - RegIO Timeout

Statistic Data Payload

Consist of fixed set of module registers:

• reg 0x004B - Board Temperature
• reg 0x004C - FPGA F/W Version
• reg 0x004D - FPGA F/W Revision
• reg 0x4001 - Onboard PLL Status
• reg 0x4002 - Onboard PLL Unlock Counter
• reg 0x4003 - PLL Temperature
• reg 0x4004 - Temperature #1 from MCU
• reg 0x4005 - Temperature #2 from MCU
• reg 0x4006 - Temperature #3 from MCU
• reg 0x4007 - Temperature #4 from MCU
• reg 0x4008 - BMC F/W Revision
• reg 0x4009 - BMC F/W Version
• reg 0x400A - BMC Overal System Status
• reg 0x400B - BMC Power Status
• reg 0x400C - BMC PLL Status

See also TDC72VXS Registers

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RawData