= TADC Hit Core Registers =

'''Base address - 0x0600, address mask - 0x00FF.'''

Reg 0x0000 - Hit Counters Control, R/W
 . [0] - Counters lock
 . [15:1] - reserved

Reg 0x0004-0x0007 - Counters Timestamp, in nanoseconds (64-bits), RO

Reg 0x0008-0x000B - Input Signal Polarity (64-bits), R/W
 . 1 - negative, 0 - positive

Reg 0x0010-0x0013 - Comparators State (64-bits), RO

Reg 0x0080-0x00FF - Channel Hit Counters, 2 registers per channel (32-bits), RO

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[[CategoryMlinkRegisters|MLinkRegisters]]