= TADC ADC Core Registers =

'''Base address - 0x0300, address mask - 0x00FF.'''

Reg 0x0000 - Latency, R/W

Reg 0x0001 - Match window, R/W

Reg 0x0002 - reserved (for prewindow)

Reg 0x0003 - ADC Window (samples to readout), R/W

Reg 0x0004 - ADC channel memory depth, in kilosamples, RO

Reg 0x0005 - ADC mode, R/W
 . [1:0]  - '0' reserved, '1' normal, '2' baseline, '3' reserved
 . [15:2] - reserved

Reg 0x0006 - Input Gain Control, R/W
 . [0]    - channels  1-2  gain: 0 - x1 gain, 1 - x4 gain
 . [1]    - channels  3-4  gain: 0 - x1 gain, 1 - x4 gain
 . [2]    - channels  5-6  gain: 0 - x1 gain, 1 - x4 gain
 . [3]    - channels  7-8  gain: 0 - x1 gain, 1 - x4 gain
 . [4]    - channels  9-10 gain: 0 - x1 gain, 1 - x4 gain
 . [5]    - channels 11-12 gain: 0 - x1 gain, 1 - x4 gain
 . [6]    - channels 13-14 gain: 0 - x1 gain, 1 - x4 gain
 . [7]    - channels 15-16 gain: 0 - x1 gain, 1 - x4 gain
 . [15:8] - reserved

Reg 0x0007 - reserved

Reg 0x0008~0x000B - Channels enable (64-bits), R/W

Reg 0x0010 - ADC Build Param 1, RO
 . [7:0] - reserved
 . [15:8] - ADC Bits

Reg 0x0011 - ADC Build Param 2, RO
 . [7:0] - ADC chips number
 . [15:8] - ADC chip channel number

Reg 0x0012 - ADC Build Param 3, RO
 . [7:0] - ADC channel ring buffer size (log2 value), in samples, defines max ADC latency
 . [15:8] - ADC channel event data buffer size (log2 value), in samples, defines max ADC match window (half of this value)

Reg 0x0013 - ADC Build Param 4, RO
 . reserved

Reg 0x0020 - ADC Pattern Test Control, R/W
 . [0] - test enable (resets previous results, when started new test)
 . [1] - pause test
 . [15:2] - reserved

Reg 0x0021 - ADC Test Pattern, msb alligned, R/W

Reg 0x0024~0x0027 - number of checked ADC words, 64-bits, RO

Reg 0x0028~0x002F - Mask of failed channels, 128-bits, RO
 . ''Bit number == channel number, set if ADC word not equal to test pattern''

Reg 0x0040~0x0043 - ADC hfifo overflow (64-bits), bit# = ch#, RO

Reg 0x0048~0x004B - ADC mfifo overflow (64-bits), bit# = ch#, RO

Reg 0x0050~0x0053 - ADC efifo overflow (64-bits), bit# = ch#, RO

Reg 0x0080~0x00FF - ADC Channel Data, one register per channel, data is msb alligned, RO

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[[CategoryMlinkRegisters|MLinkRegisters]]