## page was renamed from Spill Control Status Registers = Spill Control Module = * [[SDB Device ID]] 0x315be6df == Register Map == address space 0x00 - 0x3F || addr || bits || description || mode || default || || 00h || 32 || spill phase 1 (idle) duration, ms || R/W || 10 || || 02h || 32 || spill phase 2 (pre-burst triggers) duration || R/W || 10 || || 04h || 32 || spill phase 3 (burst triggers) duration || R/W || 3000 || || 06h || 32 || spill phase 4 (post-burst triggers) duration || R/W || 10 || || 08h || 32 || spill phase 5 (software readout) duration || R/W || 970 || || 0Ah || 32 || spill gate extension || R/W || 100 || || 0Ch || 32 || spill count (locked) || RO || || || 0Eh || 32 || current spill timer value, ms || RO || || || 10h || 32 || spill control || R/W || 0 || || 12h || 32 || spill status || RO || || || 14h || 32 || spill timer period, ms || R/W || 5000 || || 16h || 32 || spill detect min period, ms || R/W || 1000 || || 18h || 32 || spill detect max period, ms || R/W || 30000 || || 1Ah || 32 || measured last TTL spill period, ms || RO || || || 1Ch || 32 || measured last WR spill period, ms || RO || || || 1Eh ||<:-4> reserved || || 20h || 64 || last spill TAI timestamp (locked) || RO || || || 24h ||<|3-4> reserved || || ... || || 3Fh || Reg 0x10, '''spill control''', R/W . [0] softreset - clear counters and stop timers . [4:1] mode: 0 - off, 1: softspill. 2: TTL, 3: WR, 4:Infinite (since SDB ver 1.1), 7: auto, 8: gate Reg 0x12, '''spill status''', RO . [0] - TTL spill Ok . [1] - WR spill Ok . [3:2] - reserved . [5:4] - selected NCU, 0: off, 1: softspill, 2: TTL, 3: WR . [7:6] - reserved . [12:8] - current spill phase . [15:13] - reserved Spill phases: . 0 - Wait next spill . 1 - Accelerate (First spill phase) . 2 - Prepare . 4 - Spill read (Accept trig. candidates) . 8 - Post readout (Last spill phase) . 16 - Flush Reg 0x20, '''last spill TAI timestamp''' . [1:0] - {tm_time_valid, 1'b0} . [4:2] - 3'b000 . [31:5] - tm_cycles[26:0] . [63:32] - tm_tai[31:0] ---- [[CategorySDB|SDB]]