= SPI NOR Flash Memory Programmer =

HDL: https://afi-git.jinr.ru/fpga/modules/

Supported SPI Flash devices:

 * Micron
  * N25Q (128Mb, 256Mb, 512Mb)
  * MT25Q (128Mb, 256Mb, 512Mb)

=== SDB ===

 * [[SDB Device ID]] 0x6e0f7007
 * RegIO base address - 0x7000, address mask - 0x00FF.

==== Register description ver. 2.0 ====

 * 00h - Identification 0x6e0f7007, 32 bits, RO, static
 * 02h - Control, 16 bits, R/W
   . [14:0] - reserved
   . [15] - enable SPI 4-byte address mode
 * 04h - Test, unused, 16 bits, R/W
 * 05h - Command, 16 bits, R/W
 * 06h - SPI status, 16 bits, RO
 * 08h - SPI address, 16 bits, R/W
 * 0Fh - Warm boot (IPROG), 16 bits, R/W
 * 80h-FFh - SPI data, 16 bits, R/W

==== Register description ver. 1.0 ====

||<:-4> Registers ||
|| 00h || 15:0 || Control || R/W ||
|| 03h || 15:0 || Test, unused || R/W ||
|| 05h || 15:0 || Command || R/W ||
|| 06h || 15:0 || SPI status || RO ||
|| 08h || 31:0 || SPI address || R/W ||
|| 0Fh || 15:0 || Warm boot (IPROG) || R/W ||
|| 80h-FFh || 15:0 || SPI data || R/W ||

Warm boot register ''0F''

Register ''0F'' read value ''FB01'' indicates warm boot feature presence.

Write ''DEAD'' to register ''0F'' starts FPGA reconfiguration immediately (warm boot)

Software: [[https://afi-git.jinr.ru/soft/afi-dev-flash-prog|afi-dev-flash-prog]]

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[[CategorySDB|SDB]] [[CategoryFPGACore|FPGA_Core]]