## page was renamed from SdbDevices
= SDB Devices =

Unique ID generation example: {{{echo -n 'module_name version' | md5sum |cut -c -8}}}

||ID||Name||Last version||Description||
||0x3524236a||AD5328 x2 SPI||1.0||[[AD5328 x2 SPI|Two DAC AD5328 setup]]||
||0x69a3a210||ad5622_regs||1.0||[[ad5622_regs|control registers for amp. board based on AD5622]]||
||0xba3e71ca||ad9249_spi||1.0||[[Dual SPI Controller]]||
||0xfd4368fa||ADC Core||1.0||[[xxxxxx]] from TQDC SDB||
||0xa6f09c36|| ADC Info||1.0||[[ADC Info]], located in 'lib-serdes' ||
||0x286e09bb|| ADC Pattern Test||1.1||[[ADC Pattern Test]], located in 'lib-serdes' ||
||0x3ddcc6a5|| ADC CLK DIV Reset||1.0||[[ADC CLK DIV Reset]]||
||0x6c28f631||adc64wr_stat_regs||1.0||Board Statistic registers||
||0xdd07b826||ads52j90_spi||1.0||[[Dual SPI Controller]]||
||0x35f39554|| Board GPIO||1.0||[[Board GPIO]]||
||0xe89b0a06||board_mgmt_regs||1.0||Board managment registers||
||0x2c918620||calib_trig||1.0||[[Calibration triggers|Calibration triggers]]||
||0x7bc301a9||Clock Control||2.0||[[Clock Control Registers v2.0]]||
||0x5e03c11a|| Crosspoint Switch || 1.0 || [[Crosspoint Switch]] ||
||0x3efb27ee||Deserializers Contr||1.0||[[Deserializers CSR]]||
||0x6da0c416||dig_trig_csr||1.0||Trigger control registers||
||0xa5fd23ba||erc_regs||1.0||[[ADC_Event_Readout_Controller|ADC Event Readout Controller]]||
||0x371a0421||FE-Link V2.0 CSR||2.0||[[FE-Link V2.0 CSR]]||
||0x4237dc05||fir_filter_regs||1.0||[[FIR Filter]]||
||0x6e0f7007||Flash||2.0||[[SPI_NOR_Flash_Programmer]]||
||0x1492d6c0||HPTDC JTAG Controller || 1.0 || [[https://afi-project.jinr.ru/projects/hptdc-jtag-controller/wiki|HPTDC Controller Registers]] ||
||0x2a2a5a63||HWIP Error Counters||1.0||[[HWIP_Error_Counters|HWIP Error Counters v1.0]]||
||0x2324ece4|| Input Hit Core||1.0||[[TADC System Hit Core Registers|Input Hit Core]] ||
||0x2e0160f8||lemo_control_regs||1.0||[[LEMO_control_register|LEMO control register]]||
||0xde2766bc||LTM9011 x2 SPI||1.0||tqdc16vs regio_spi_ltm9011_dual||
||0x8df3221b||MCU||1.0||[[xxxxxx]] from TQDC SDB||
||0x47567e3c||MCU||2.0||[[MCU Registers v2.0]]||
||0x50b1d9c7||MLink TADC CSR||1.0||[[MlinkCsr]]||
||0x41a37c29||MLink-CSR||1.0||[[MlinkCsr]]||
||0x8a3b62cd||MPD TRC Core||1.0||[[MPD TRC Core]]||
||0x77268a46||MSC Cycle Counters||1.0||[[MSC Cycle counters CSR]]||
||0x8da907fb||MSC Histograms||2.0||[[MSC Histograms CSR v2.0]]||
||0xd26e4053||MSC Input||1.0||[[MSC Input CSR]]||
||0xfd880c84||MSC Stream Readout||1.0||[[MSC Stream readout CSR v1.0]]||
||0xc3bcc4aa||MSC onboard||1.0|| [[MSC onboard CSR]] ||
||0xe050724f||Network Port||2.0||[[Network Port Registers]] ||
||0xf4da37e8|| Run Logic||1.0||[[Run Logic]] ||
||0x5d28c101||Run Statistic Module||1.0||[[Run Statistic Module]] ||
||0x9d754a61||SDB||1.1||SDB ROM data||
||0x315be6df|| Spill Control||1.0||[[Spill Control Module]] ||
||0xfb0bcd7f||Statistics Readout Control||1.0||[[Statistics Readout Module v1.0]] ||
||0x891f9f31||TRC ERC||1.0||[[UT24VE-TRC-Registers#ERC_REG|TRC Event Readout Controller]]||
||0xe347158d||TRC System||1.0||[[UT24VE-TRC-Registers#SYS_REGS|PHY TRIG System registers]]  ||
||0x76b80b88|| Trigger Control||1.0||[[Trigger Control]] ||
||0x510dbe12|| Trigger Info||1.0||[[TrigInfo]] ||
||0x8857c5c8||TQDC16VS TTL IO Control||1.0||[[xxxxxx]] from TQDC SDB||
||0x30f132b5||UT24VE TTL I/O Control||1.0||[[UT24VE TTL I/O Control]]||
||0xc32e925e|| Waveform BLC || 1.1 || [[Waveform BLC]] ||
||0x7477e01e|| Waveform Recorder||2.1||[[Waveform Recorder Module]] ||
||0x3d1ca270|| Waveform Trig || 1.0 || [[Waveform Trig]] ||
||0xe5ea34bf||WR Status||1.0||[[WR_Status_Registers|White Rabbit Endpoint State Registers v1.0]] ||
||0x60120c01||WR Time Emulator||2.0||[[WR Time Emulator]] ||
||0x2fc0a72a||zs_regs||1.0||[[ZS_Registers|active ZS channels for adc64 prog.]]||

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[[CategorySDB|SDB]]