= MStream Core 2.x =

Part of [[Network Port Registers]]

||<:-4> Registers ||
|| 00h || 31:0 || Identification ''4D533278h'' || RO ||
|| 02h || 31:0 || Control || R/W ||
|| 04h || 31:0 || Status || RO ||
|| 06h || 15:0 || Minimal MTU || RO ||
|| 07h || 15:0 || Maximal MTU || RO ||
|| 08h || 15:0 || MTU || R/W ||
|| 09h || 15:0 || Max packet size, bytes || R/W ||
|| 0Ah || 19:0 || defragmentation timeout, microseconds || R/W ||
||<-4> ||
|| 10h || 31:0 || RETX ack time || RO ||
|| 12h || 31:0 || RETX config || RO ||
|| 14h || 31:0 || RETX estimated RTT || RO ||
||<-4> ||
|| 1Eh || 31:0 || Clock frequency, kHz || RO ||
|| 20h-3Fh || 31:0 || 16 counters || RO ||
|| 40h-4Fh || 31:0 || 8 timers || RO ||
|| 50h-7Fh ||<-3> ||


Timer resolution is 1 second.

==== Register description ====

||<:-2> Status register bits ||
|| 15:0 || reserved ||
|| 23:16 || MStream version minor ||
|| 31:24 || MStream version major ||

||<:-2> mstream control bits ||
|| 1:0 || clear buffers: write ''2'' to clear ||
||<-4> ||

||<:-2> RETX config bits ||
|| 3:0 || number of buffers, log2 ||
|| 7:4 || buffer address bits (9: normal, 11: jumbo 8k) ||
||<-4> ||

==== Counters ====

|| 0 || Input word ||
|| 1 || RETX output word ||
|| 2 || Input packet ||
|| 3 || Split packet ||
|| 4 || Merged packet ||
|| 5 || Passed (timeout) packet ||
|| 6 || Passed (no more space) packet ||
|| 7 || RETX input packet ||
|| 8 || RETX output packet ||
|| 9 || RETX retransmitted packet ||
|| 10 || RETX received ACK ||
|| 11 || RETX timeout ||
|| 12 || RETX overflow ||
|| 13 || Input header error ||
|| 14 || Input length error ||
|| 15 || Input data error ||

==== Timers ====

|| 0 || Uptime ||
|| 1 || Input packet ||
|| 2 || Concatenated packet ||
|| 3 || RETX output packet ||
|| 4 || RETX received ACK ||
|| 5 || RETX overflow ||
|| 6 || RETX timeout ||
|| 7 || RETX buffer overrun ||

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[[CategoryMStream|MStream]] [[CategoryMlinkRegisters|MLinkRegisters]] [[CategorySDB|SDB]] [[CategoryFPGACore|FPGA_Core]]