= MSC16VE Memory Adress Map v2 =

Hardware [[MSC16VE]]

See also [[MSC16VE-EthRegisters_v2|Ethernet registers v2]]

||<:>Address range||<:>Description ||
|| 0x0~0x1FFFF           || [[#TIH|Time interval histograms]] ||
|| 0x20000~0x3FFFF       || [[#PLOT|Plot histograms]] ||

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<<Anchor(TIH)>>

=== Time interval histograms ===

''Base address 0x0''

Number of address bits for each histogram are stored in [[MSC16VE-EthRegisters_v2#HIST|Histogram CSR]] register 0x14

@0x0~0x3FF - time interval histogram #0

@0x400~0x7FF - time interval histogram #1

@0x800~0xBFF - time interval histogram #2

@0xC00~0xFFF - time interval histogram #3

@0x1000~0x13FF - time interval histogram #4

@0x1400~0x17FF - time interval histogram #5

@0x1800~0x1BFF - time interval histogram #6

@0x1C00~0x1FFF - time interval histogram #7

@0x2000~0x23FF - time interval histogram #8

@0x2400~0x27FF - time interval histogram #9

@0x2800~0x2BFF - time interval histogram #10

@0x2C00~0x2FFF - time interval histogram #11

@0x3000~0x33FF - time interval histogram #12

@0x3400~0x37FF - time interval histogram #13

@0x3800~0x3BFF - time interval histogram #14

@0x3C00~0x3FFF - time interval histogram #15

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<<Anchor(PLOT)>>

=== Plot histograms ===

''Base address 0x20000''

Number of address bits for each histogram are stored in [[MSC16VE-EthRegisters_v2#HIST|Histogram CSR]] register 0x8

@0x0~0x1FFF - plot histogram #0

@0x2000~0x3FFF - plot histogram #1

@0x4000~0x5FFF - plot histogram #2

@0x6000~0x7FFF - plot histogram #3

@0x8000~0x9FFF - plot histogram #4

@0xA000~0xBFFF - plot histogram #5

@0xC000~0xDFFF - plot histogram #6

@0xE000~0xFFFF - plot histogram #7

@0x10000~0x11FFF - plot histogram #8

@0x12000~0x13FFF - plot histogram #9

@0x14000~0x15FFF - plot histogram #10

@0x16000~0x17FFF - plot histogram #11

@0x18000~0x19FFF - plot histogram #12

@0x1A000~0x1BFFF - plot histogram #13

@0x1C000~0x1DFFF - plot histogram #14

@0x1E000~0x1FFFF - plot histogram #15