= MSC Histograms CSR v2.0 =

 * [[SDB Device ID]] 0x8da907fb
 * [[MSC Histograms CSR v1.0]]

==== Register Map ====

 * 00h - '''Identification''' ''8da907fb'', 32 bits, RO

 * 02h - '''Control''', R/W
   . [0] - reset

 * 03h - '''Lock''', R/W

   . [0] - update (1: lock, 0: continuous update)

 * 04h - '''Clock frequency Hz''', 32 bits, RO

 * 06h - '''Number of channels (hists) per group''', RO

 * 07h - reserved

 * 08h - '''RAM address of logarithmic histograms''', 32 bits, RO

 * 0Ah - '''Number of RAM address bits per logarithmic histogram''', RO

 * 0Bh - reserved

 * 0Ch - '''Logarithmic histogram registers''' address, RO

 * 0Dh~0Fh - reserved

 * 10h - '''RAM address of plot histograms''', 32 bits, RO

 * 12h - '''Number of RAM address bits per plot histogram''', RO

 * 13h - reserved

 * 14h - '''Plot histogram registers''' array address, RO

 * 15h - '''Plot histogram registers address mask''' of array element, RO

==== Logarithmic histogram registers ====

 * 00h - '''Logarithmic histograms parameter #1''' (0x3F800000, 1.0 float, DO NOT CHANGE), 32 bits, R/W
 * 02h - '''Logarithmic histograms parameter #2''' (0x42580000, 54.0 float, DO NOT CHANGE), 32 bits, R/W
 * 04h - '''Logarithmic histograms type mask''', 32 bits, R/W
  * '0' - time interval histogram, '1' - time length histogram

==== Plot histogram registers array ====

''Each plot histogram has its own set of registers''

 * 00h - '''plot slice time (in nanoseconds)''', 32-bits, R/W
 * 02h - '''plot current RAM address''', 32-bits, RO
 * 04h - '''plot last RAM address of previous gate''', 32-bits, RO
 * 06h - '''plot last RAM address of previous cycle''', 32-bits, RO
 * 08h - '''gate number''', 32-bits, RO