= MSC Cycle counters CSR =

 * [[SDB Device ID]] 0x77268a46
 * Hardware [[MSC16VE]]
 * [[MSC16VE-EthRegisters_v2|MSC16VE Registers]]

=== Registers ===

 * 00h - '''Control''', R/W
  . [0] - softclear
  . [1] - counters lock
 * 01h - '''Number of channels''', RO
 * 04h - '''Current state of cycles''', 64-bits, RO

''__Start from address 0x10__ groups of cycle counters are placed. One group - one histogram channel. Each group size is 16 addresses. All registers are read only''

Regs 10h~1Fh - Histogram #0 registers group
 . 10h - '''counts during active gate''', 32-bits, RO
 . 12h - '''counts for full cycle''' (active + inactive gate), 32-bits, RO
 . 14h - '''last gate start time''', [[TAI 64-bit Timestamp]], 64-bits, RO
 . 18h - '''last gate end time''', [[TAI 64-bit Timestamp]], 64-bits, RO
 . 1Ch - '''gate number''', 32-bits, RO
 . 1Eh - reserved
 . 1Fh - reserved

Regs 20h~2Fh - Histogram #1 registers group

...

Regs 100h~10Fh - Histogram #15 registers group

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[[CategoryMSC|MSC]]  [[CategorySDB|SDB]]