MAC CSR 2.0
Part of Network Port Registers
Versions
- 2.0
Identification 58bc2e51
- Counters base address changed 10h to 20h
- Add status bits 12, 13
- 1.0 - Initial version
Identification 8b9a8b2b
Registers
Registers |
|||
00h |
31:0 |
Identification 58bc2e51 |
RO |
02h |
31:0 |
Control |
R/W |
04h |
31:0 |
Status |
RO |
06h |
15:0 |
MTU size, bytes |
RO |
|
|||
20h-3Fh |
31:0 |
16 32-bit counters |
RO |
Counters
# |
Base |
Description |
0 |
20 |
RX frame |
1 |
22 |
RX error |
2 |
24 |
TX frame |
3 |
26 |
TX error |
4 |
28 |
RX CRC error |
5 |
2A |
RX pause frame |
6 |
2C |
local fault |
7 |
2E |
remote fault |
8 |
30 |
RX MAC FIFO overrun |
9 |
32 |
RX MAC FIFO underrun |
10 |
34 |
TX MAC FIFO overrun |
11 |
36 |
TX MAC FIFO underrun |
12 |
38 |
RX FIFO overrun |
13 |
3A |
TX FIFO overrun |
14 |
3C |
... |
15 |
3E |
... |
Register description
Status register
status register is used internally for counters (counts transition 0-to-1)
Status register bits |
|
0 |
RX frame |
1 |
RX error |
2 |
TX frame |
3 |
TX error |
4 |
CRC error |
5 |
Pause frame received |
6 |
local fault |
7 |
remote fault |
8 |
RX MAC FIFO overrun |
9 |
RX MAC FIFO underrun |
10 |
TX MAC FIFO overrun |
11 |
TX MAC FIFO underrun |
12 |
RX FIFO overrun |
13 |
TX FIFO overrun |
|
|
Note: status bits [13:4] available form 10G (xge_mac) only