= HWIP CSR 1.0 =

Part of [[Network Port Registers]]

||<:-4> Registers ||
|| 00h || 31:0 || Identification || RO ||
|| 02h || 31:0 || Control || R/W ||
|| 04h || 31:0 || Status || RO ||
|| 06h || 31:0 || Host IPv4 address || RO ||
|| 08h || 47:0 || Host MAC address || RO ||
|| 0Ch || 31:0 || RegIO bus error address || RO ||
|| 0Eh || 31:0 || RegIO bus error code || RO ||
||<-4> ||
|| 10h || 31:0 || mlink control || R/W ||
|| 12h || 31:0 || master peer IPv4 address || RO ||
|| 14h || 15:0 || master peer UDP port || RO ||
||<-4> ||
|| 18h || 31:0 || mstream control || R/W ||
|| 1Ah || 31:0 || mstream peer IPv4 address || RO ||
|| 1Ch || 15:0 || mstream peer UDP port || RO ||
|| 1Dh || 15:0 || MTU || R/W ||
|| 1Eh || 19:0 || defragmentation timeout, microseconds || R/W ||
||<-4> ||
|| 30h || 31:0 || RETX ack time || RO ||
|| 32h || 31:0 || RETX config || RO ||
|| 34h || 31:0 || RETX estimated RTT || RO ||
||<-4> ||
|| 40h || 31:0 || RegIO error counter || RO ||
|| 42h || 31:0 || RegIO timeout counter || RO ||
|| 42h || 31:0 || RETX buffer overrun counter || RO ||
||<-4> ||
|| 50h || 31:0 || Uptime timer || RO ||
|| 52h || 31:0 || IP assign (DHCP lease) timer || RO ||
|| 54h || 31:0 || master lock timer || RO ||
|| 56h || 31:0 || mstream lock timer || RO ||
|| 58h || 31:0 || RegIO error timer || RO ||
|| 5Ah || 31:0 || RegIO timeout timer || RO ||
|| 5Ch || 31:0 || RETX buffer overrun timer || RO ||

Timer resolution is 1 second.

==== Register description ====

||<:-2> Status register bits ||
|| 0 || IP assigned (DHCP leased) ||
|| 1 || master locked ||
|| 2 || mstream locked ||
|| 3 || RegIO error ||
|| 4 || RegIO timeout ||
|| 5 || RETX buffer overrun ||
||<-4> ||


||<:-2> RegIO bus error code bits ||
|| 0 || write changed while strobe ||
|| 1 || addr changed while strobe ||
|| 2 || wdata changed while strobe ||
|| 3 || rdata changed while strobe ||
|| 4 || rdy deasserted while strobe ||
|| 5 || cycle aborted ||


||<:-2> mlink control bits ||
||<-4> ||

||<:-2> mstream control bits ||
|| 0 || stream reset mode: 0 - legacy, 1 - use  bit 1 ||
|| 1 || stream_reset ||
||<-4> ||

||<:-2> RETX config bits ||
|| 3:0 || number of buffers, log2 ||
|| 7:4 || buffer address bits (9: normal, 11: jumbo 8k) ||
||<-4> ||

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[[CategoryMlinkRegisters|MLinkRegisters]] [[CategorySDB|SDB]] [[CategoryFPGACore|FPGA_Core]]