= FVME2TM, FVME2TMWR =

<<TableOfContents>>

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FVME2TM is a Trigger, Timing and Control Module for [[VMEDAQ]] system. It is a successor of [[TTCM]] module. It is a 6U VME64x slave module. FVME2TM has onboard 41.667 MHz clock generator that is used for clock source for [[TTC]] bus. FVME2TM has TTL level LEMO inputs for spill and trigger signals and 32 ECL/LVDS inputs for trigger signals. Two TTL level LEMO outputs are software programmable. TTL inputs has 50 Ohm internal termination. TTL outputs are capable of driving 50 Ohm load.

FVME2TMWR is a FVME2TM board with [[WhiteRabbit|White Rabbit]] support.

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== Front Panel Interfaces ==

{{attachment:fvme2tm_v2_260x800_descr.png}}

=== Inputs/Outputs ===

 . LEMO 1 - SPILL input. External sync signal, positive logic. Readout enabled with logic one on this input.
 . LEMO 2 - TRIG input, 5 ns minimum
 . LEMO 3 - lemo_XOFF input OR programmable output1
 . LEMO 4 - programmable output2
 . LVDS1..LVDS32 - Trigger inputs, LVDS or ECL, 5 ns minimum

=== Status LEDs ===

FVME2TM front panel has 12 LEDs with the following layout:

||<:-3>LEDs||Function||
||G||Y||R||trig read, trig block, spill||
||G||Y||R||vme run, vme activity, vme error||
||G||Y||R||||
||G||Y||R||SFP leds||

== VME Interface ==

=== VME Interrupt Lines ===
 . IRQ1 - data read XOFF input

=== VME Registers ===
 * Detailed description of [[VmeRegistersTtcm|TTCM VME Registers]]

=== VME Data Format ===
 * [[DataFormatTTCM|TTCM Raw Data Format]]
 * [[DataFormatFVME2TMWR|FVME2TMWR Raw Data Format]]

== Clock and Synchronization ==

[[attachment:fvme2tmwr_clk.png|{{attachment:fvme2tmwr_clk_512px.png}}]]

== Trigger Cable ==
For use with [[TQDC-16]], special ribbon twisted pair cable is supplied with 34-pin connector on one side and four 10-pin connectors on other side. One cable connects four TQDC-16 modules with TTCM.

== Input Aggregation ==
Trigger inputs are combined after shaping and delay by OR scheme. 40 inputs are reduced to 4 trigger lines. Logic OR is performed this way (trigger line = input OR input ...):
 . ST = LVDS1
 . TQDC1 = LVDS6 | LVDS10 | LVDS14
 . TQDC2 = LVDS18 | LVDS22 | LVDS26 | LVDS30
 . NIM = NIM1 | ... | NIM7

== Trigger Logic Delay ==

Measured delay from NIM input to TTC bus output: min. 530 ns, max. 580 ns. Due to 20 MHz sampling the delay is varied by 50 ns. this applies to TTCM firmware 1.0.10604

<<Include(TTC)>>

== Registers (Ethernet access) ==

[[FVME2TMWR_Ethernet_Registers]]

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[[CategoryLogic|Logic]] [[CategoryVme|VME]] [[CategoryTTC|TTC]] [[CategoryEthernet|Ethernet]] [[CategoryWhiteRabbit|WhiteRabbit]]