= FE-Link V2.0 CSR =

[[https://afi-project.jinr.ru/projects/fe-link/wiki/Wiki|FE-Link Wiki]]

[[felink_v1_csr|FE-Link V1.0 CSR]]

 * [[SDB Device ID]] 0x371a0421

==== Register map ====

 * 00h, '''Identification''' ''371a0421'', 32 bits, RO static
 * 02h, '''Control''', R/W
   . [0] - reset
 * 03h, '''Lock''', R/W
   . [0] - 1: lock, 0: continuous update
 * 04h, '''Number of channels''', RO static
 * 05h, '''Address of 1^st^ FE-Link channel registers''', RO static
 * 06h, '''Log2 address space per one FE-Link channel''', RO static

==== One FE-Link channel registers ====

 * 00h, '''Control''', R/W
   . [0]    - channel enable (enabled by default)
   . [1]    - manual phase adjust enable (enabled by default)
   . [2]    - automatic phase adjust enable (enabled by default, higher priority than manual)
   . [3]    - recv trigger enable (enabled for slave, disable for master by default)
   . [13:4] - reserved
   . [14]   - reset statistics (counters)
   . [15]   - reset softpll
 * 01h, '''PHY level control''', R/W
   . [0]    - manual reset PHY level
   . [1]    - enable automatic PHY reset (enabled by default)
   . [2]    - self-release PHY level reset (activated by changing from '0' to '1')
   . [15:3] - reserved
 * 02h, '''Channel info''', 32 bits, RO static
   . [7:0]   - channel number
   . [15:8]  - reserved
   . [23:16] - VXS slot number or SFP connector number (depends on communication environment code, [[#QSFP_BITS|decoding]])
   . [27:24] - communication environment code (0: QSFP, 1: SFP, 2: VXS, other: reserved)
   . [30:28] - reserved
   . [31]    - is master
 * 04h, '''FE-Link protocol version''', RO static
   . [3:0]  - minor version
   . [7:4]  - major version
   . [15:8] - reserved
 * 05h, '''Status''', RO
   . [0]    - PHY level sync
   . [1]    - rx sync (remote device PHY level sync)
   . [2]    - remote rx sync (remote device verified our PHY level sync)
   . [3]    - softpll locked (only for time receiving side)
   . [4]    - link ok
   . [7:5]  - reserved
   . [8]    - SFP inserted (inverted SFP_MOD_DETECT)
   . [9]    - SFP Signal Detect (inverted SFP_LOS)
   . [10]   - SFP_TX_FAULT
   . [11]   - SFP_TX_DISABLE
   . [14:12] - reserved
   . [15]   - phase adjust enabled
 * 06h, '''RX Bitslide''', RO
 * 07h, '''Remote Protocol Version''', RO
   . [3:0]  - minor version
   . [7:4]  - major version
   . [15:8] - reserved
 * 08h, '''Remote ID''', 64 bits, RO
   . [47:0]  - Serial ID
   . [55:48] - [[DeviceId|Device ID]]
   . [63:56] - reserved
 * 0Ch, '''Remote channel info''', 32 bits, RO 
   . [7:0]   - channel number
   . [15:8]  - reserved
   . [23:16] - VME slot number, QSFP or SFP connector number (depends on communication environment code, [[#QSFP_BITS|decoding]])
   . [30:24] - reserved
   . [31]    - is master
 * 0Eh~0Fh, reserved
 * 10h, '''TAI seconds''', 64 bits, RO (''only for time receiving side'')
 * 14h, '''TAI nanoseconds''', 32 bits, RO (''only for time receiving side'')
   . [0]    - 0
   . [1]    - time valid
   . [31:2] - nanoseconds
 * 16h~17h, reserved
 * 18h, '''Current link state time''', ''milliseconds'', 32 bits, RO
 * 1Ah, '''SYNC resend time''', ''milliseconds'', 107 ms by default, R/W
 * 1Bh, '''SYNC receive timeout''', ''milliseconds'', 2000 ms by default, R/W
 * 1Ch, '''Timeout for time frame receiving''', ''milliseconds'', 3000 ms by default, R/W
 * 1Dh, '''Counter up step for received bad packets''', default 10, R/W
 * 1Eh, '''Bad packets counter threshold''', default 99, R/W
 * 1Fh, reserved
 * 20h, '''GTX Control''', 32 bits, R/W
    . [0]    - GTX reset
    . [3:1]  - LOOPBACK
    . [5:4]  - RXPD
    . [7:6]  - TXPD
    . [8]    - enable gtxe2c_txphalign module
    . [31:9] - reserved
 * 22h, '''GTX Status''', 32 bits, RO
    . [2:0]   - encoded CPLL reset state
    . [3]     - CPLLLOCK
    . [4]     - CPLLREFCLKLOST
    . [5]     - CPLLPD
    . [6]     - CPLLRESET
    . [7]     - CPLL ready
    . [10:8]  - encoded TX reset state
    . [11]    - TX ready
    . [12]    - TX reset done
    . [13]    - GTTXRESET
    . [16:14] - encoded RX reset state
    . [17]    - RX ready
    . [18]    - RX reset done
    . [19]    - GTRXRESET
    . [20]    - RX CDR lock
    . [21]    - RX comma detect
    . [22]    - RX byte alligned
    . [23]    - RX synced
    . [24]    - GTX ready
    . [31:25] - reserved
 * 23h~3Fh, reserved

''Registers 40h~7Fh are for 32 bits counter''

 * 40h, '''RX code error counter''', 32 bits, RO
 * 42h, '''RX CRC error counter''', 32 bits, RO
 * 44h, '''SYNC frame sent counter''', 32 bits, RO
 * 46h, '''SYNC frame received counter''', 32 bits, RO
 * 48h, '''TIME frame sent counter''', 32 bits, RO
 * 4Ah, '''TIME frame received counter''', 32 bits, RO
 * 4Ch, '''TRIG frame sent counter''', 32 bits, RO
 * 4Eh, '''TRIG frame received counter''', 32 bits, RO
 * 50h, '''XOFF frame sent counter''', 32 bits, RO
 * 52h, '''XOFF frame received counter''', 32 bits, RO
 * 54h, '''DATA frame sent counter''', 32 bits, RO
 * 56h, '''DATA frame received counter''', 32 bits, RO
 * 58h, '''Unknown frame received counter''', 32 bits, RO
 * 5Ah, '''Reset PHY counter''', 32 bits, RO
 * 5Ch~7F, reserved

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<<Anchor(QSFP_BITS)>>

'''QSFP channel decoding''' ''(bits [23:16] of local and remote channel info registers 0x2 and 0xC)''

||7||6||5||4||3||2||1||0||
||<:-4>QSFP number||<:-4>QSFP channel||

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[[CategorySDB|SDB]]